PLL Timing Pulse Generation for Low-Jitter Optical Measurement
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Solution Overview
Problem
Existing optical measurement systems for neural activity detection face challenges in generating precise and consistent timing pulses, particularly in minimizing circuitry, power consumption, and jitter, especially when using delay locked loop (DLL) circuits, which are complex and prone to misalignment due to temperature and voltage variations.
Innovation Solution
The implementation of phase lock loop (PLL) circuit-based signal generation architectures, which leverage PLL feedback divider and voltage-controlled oscillator states to produce precise, programmable timing pulses with minimal jitter, reducing the need for extensive circuitry and minimizing the impact of temperature and voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay locked loop (DLL) circuits are used for signal generation, then timing pulse generation is achieved, but circuit complexity increases and jitter increases due to temperature and voltage variations
Solution Approach 1:
The patent replaces the mechanical/electrical delay locked loop (DLL) circuit with a phase lock loop (PLL) circuit based architecture. This substitution fundamentally changes the signal generation mechanism, using PLL's voltage-controlled oscillator and feedback divider instead of DLL's delay elements, thereby reducing circuit complexity while maintaining or improving timing precision.
Solution Approach 2:
The patent employs feedback mechanisms within the PLL circuit, where the output signal is fed back through a feedback divider to the phase detector. This closed-loop feedback system automatically compensates for timing errors and reduces jitter caused by temperature and voltage variations, improving measurement precision without requiring complex external circuitry.
2Measurement precision
If delay locked loop (DLL) circuits are used for signal generation, then timing pulse generation is achieved, but power consumption increases due to extensive circuitry
Solution Approach 1:
The patent substitutes the power-hungry DLL circuit with a more efficient PLL-based architecture. The PLL circuit uses a voltage-controlled oscillator and feedback mechanism that consumes less power while achieving the same timing pulse generation function, thereby reducing overall system power consumption.
Solution Approach 2:
The patent changes the operational parameters of the signal generation system by using PLL instead of DLL. This parameter change includes using frequency division and phase detection mechanisms that are inherently more power-efficient than the delay-based approach of DLL circuits, reducing power consumption while maintaining timing precision.
3Reliability
If delay locked loop (DLL) circuits are used for signal generation, then timing pulse generation is achieved, but jitter increases due to temperature and voltage variations
Solution Approach 1:
The patent uses feedback in the PLL circuit where the output is divided and fed back to compare with the reference signal. This feedback mechanism continuously corrects phase and frequency deviations caused by temperature and voltage variations, reducing jitter and improving both reliability and measurement precision of the timing pulses.
Solution Approach 2:
The patent changes the system's operational approach by using PLL's phase and frequency control parameters instead of DLL's delay parameters. This parameter change makes the system more robust against environmental variations, as PLL can dynamically adjust its parameters to maintain signal consistency and reduce jitter.
4Device complexity
If phase lock loop (PLL) circuit-based signal generation is implemented, then circuit complexity is reduced, but implementation complexity arises due to PLL feedback divider and voltage-controlled oscillator states
Solution Approach 1:
The patent makes the PLL circuit multi-functional by using the same feedback divider and voltage-controlled oscillator states for multiple purposes: generating timing pulses, providing clock signals, and enabling precise timestamp generation. This universality reduces the need for separate dedicated circuits, simplifying implementation despite the PLL's inherent complexity.
Solution Approach 2:
The patent enables the PLL circuit to self-configure and self-synchronize using its internal feedback mechanisms. The voltage-controlled oscillator and feedback divider work together automatically to lock onto the reference frequency and generate the required timing signals, reducing the need for external adjustment and simplifying manufacturing and implementation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables robust and accurate timestamp signal generation and distribution, reducing circuit complexity, power consumption, and jitter, while maintaining precision across varying conditions, thus enhancing the reliability of optical measurement systems for neural activity detection.
Implementation Method 1
a voltage controlled oscillator configured to lock to the reference clock and having a plurality of stages configured to output a plurality of fine phase signals each having a different phase
Data Source
AI summary
An exemplary system includes a PLL circuit and a precision timing circuit connected to the PLL circuit. The PLL circuit has a PLL feedback period defined by a reference clock and includes a voltage controlled oscillator configured to lock to the reference clock and having a plurality of stages configured to output a plurality of fine phase signals each having a different phase, and a feedback divider configured to be clocked by a single fine phase signal included in the plurality of fine phase signals and have a plurality of feedback divider states during the PLL feedback period. The precision timing circuit is configured to generate a timing pulse and set, based on a first combination of one of the fine phase signals and one of the feedback divider states, a temporal position of the timing pulse within the PLL feedback period.