PLL Phase Alignment Using Output Clock Toggle Suppression
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Solution Overview
Problem
Conventional phase-locked loops (PLLs) face a lengthy phase alignment process, which can act as a bottleneck for overall locking operation and result in increased power consumption.
Innovation Solution
The improved PLL design includes a circuit that quickly reduces initial phase errors by preventing the output clock signal from toggling during a specific time interval, allowing for faster phase alignment and reduced power consumption by sampling edges of feedback and input clock signals to control the toggling of the output clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional phase alignment operation is used in digital PLLs and low bandwidth PLLs, then phase alignment can be achieved, but the process becomes lengthy and creates a bottleneck for overall locking operation
Solution Approach 1:
The patent applies preliminary action by performing a coarse phase alignment before the fine phase alignment. The coarse alignment circuit quickly reduces the initial phase error to a smaller range, preparing the system for the subsequent fine alignment process. This preliminary coarse alignment reduces the time required for the overall phase alignment operation while maintaining accuracy.
2Measurement precision
If conventional phase alignment operation is used in digital PLLs and low bandwidth PLLs, then phase alignment can be achieved, but power consumption increases
Solution Approach 1:
The patent segments the phase alignment process into two distinct stages: coarse phase alignment and fine phase alignment. Each stage uses different circuits optimized for its specific function. The coarse alignment circuit handles large phase errors with lower power consumption, while the fine alignment circuit handles small phase errors with higher precision. This segmentation reduces overall power consumption by matching circuit complexity to the alignment stage requirements.
3Productivity
If the output clock signal continues to toggle during phase alignment, then continuous clock operation is maintained, but phase alignment time increases
Solution Approach 1:
The patent applies dynamics by making the output clock signal toggling behavior adaptive based on the alignment stage. During coarse alignment, the output clock signal toggling is controlled or paused to allow rapid phase error reduction. During fine alignment, the toggling is restored or adjusted to maintain clock continuity while achieving precise phase alignment. This dynamic control optimizes both locking speed and clock reliability.
Data Source
AI summary
Some embodiments include apparatuses and methods of operating such apparatuses. One of the apparatuses includes a first circuit included in a phase-locked loop (PLL) to receive an input clock signal and a feedback clock signal, and to generate an output clock signal; a second circuit included in the PLL to generate the feedback clock signal from the output clock signal; and a third circuit to prevent the output clock signal from toggling during a portion of a time interval when the PLL performs an operation of aligning phases of the input clock signal and feedback clock signal.