Two-Point Frequency Search PLL Control Settling Time
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Solution Overview
Problem
Existing phase-locked loop (PLL) architectures face challenges in reducing settling time, which is critical for system startup, as they often require significant time for the output frequency to converge to the programmed frequency.
Innovation Solution
The implementation of a hybrid digital and analog control method within the PLL, which includes open-loop digital control for estimating the control value and closed-loop analog control for converging the frequency to the programmed value, significantly reduces settling time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional PLL control methods are used, then the PLL can maintain stable frequency operation, but the settling time is long (180 microseconds or more)
Solution Approach 1:
The patent applies preliminary action by performing a two-point frequency search before final frequency locking. The system pre-determines two frequency points and their corresponding control codes, then uses these pre-acquired data points to calculate the optimal control code for the target frequency. This preliminary frequency characterization enables faster convergence without sacrificing stability.
Solution Approach 2:
The patent segments the frequency locking process into distinct phases: initial frequency search phase (acquiring two frequency points), calculation phase (determining control code relationship), and convergence phase (applying control code to reach target frequency). This segmentation allows each phase to be optimized independently, with the search phase gathering necessary data and the convergence phase rapidly achieving the target.
2Speed
If the PLL uses a simple control loop, then the circuit complexity is reduced, but the frequency convergence speed decreases
Solution Approach 1:
The patent replaces traditional mechanical/analog feedback control mechanisms with a digital calculation-based control system. Instead of relying solely on analog phase-locked loop components for frequency adjustment, the system uses digital frequency measurement, mathematical calculation of control codes, and digital-to-analog conversion. This substitution enables faster response times while keeping the overall circuit architecture relatively simple.
Solution Approach 2:
The patent changes the control parameter from direct analog voltage adjustment to digital control code manipulation. By measuring frequencies at two distinct control code points and calculating the linear relationship between control codes and frequencies, the system can predict the optimal control code for any target frequency. This parameter transformation enables rapid convergence through computational rather than iterative adjustment.
Data Source
AI summary
In an example, a phase-locked loop (PLL) circuit includes an oscillator, a frequency search circuit, and an analog control loop. The oscillator is configured to provide a clock signal. The frequency search circuit is configured to measure a first frequency of the clock signal for a first clock control signal, measure a second frequency of a second signal for a second clock control signal, and determine, based on the first frequency, the second frequency, the first clock control signal, and the second clock control signal, a third clock control signal corresponding to a programmed frequency, the third clock control signal for causing the clock signal to have a frequency based on the programmed frequency. The analog control loop is configured to control the oscillator to cause the frequency to converge to the programmed frequency.