PLL VCO Frequency Calibration Using Multi-Mode Clock Measurement
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Solution Overview
Problem
Existing phase lock loop (PLL) circuits require substantial additional circuitry and power for frequency calibration of voltage controlled oscillators (VCOs), leading to increased IC footprint and lengthy calibration procedures, which are inefficient in terms of power consumption and calibration time.
Innovation Solution
A selection mode device is integrated into the PLL to facilitate separate frequency measurements of reference and feedback clock signals, allowing for coarse frequency calibration using existing components, reducing the need for additional circuitry and power, and enabling faster calibration with higher resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional calibration circuits are used to set initial VCO frequency, then frequency calibration capability is achieved, but circuit complexity and power consumption increase substantially
Solution Approach 1:
The patent combines the frequency calibration function with the existing phase detector and frequency divider components of the PLL circuit. The phase detector is configured to receive either the reference clock signal or the feedback clock signal, eliminating the need for separate calibration circuitry while achieving frequency calibration through the existing PLL architecture.
Solution Approach 2:
The phase detector is designed to perform multiple functions: it operates in calibration mode to measure frequency by receiving the feedback clock signal, and in normal operation mode to detect phase difference by receiving the reference clock signal. This multi-functionality eliminates the need for dedicated calibration electronics.
2Measurement precision
If traditional calibration circuits are used to set initial VCO frequency, then frequency calibration capability is achieved, but power consumption increases
Solution Approach 1:
The calibration function is merged with the existing phase detector and frequency divider components that are already powered during normal PLL operation. By configuring these existing components to perform calibration measurements, the patent avoids powering additional dedicated calibration circuitry, thereby reducing overall power consumption.
Solution Approach 2:
The PLL circuit uses its own existing components (phase detector, frequency divider, VCO) to perform frequency calibration without requiring external or additional calibration circuits. The system calibrates itself by utilizing the feedback clock signal through the existing phase detector, eliminating the need for separate power-consuming calibration electronics.
3Measurement precision
If traditional calibration circuits are used to set initial VCO frequency, then frequency calibration capability is achieved, but calibration time increases
Solution Approach 1:
The patent performs frequency calibration as a preliminary step before normal PLL operation by configuring the phase detector to receive the feedback clock signal and measure its frequency. The calibration controller determines the frequency range based on this measurement and pre-adjusts the VCO control voltage, enabling faster convergence during subsequent normal operation and reducing overall calibration time.
Solution Approach 2:
By using the existing frequency divider and phase detector to quickly measure the feedback clock signal frequency and determine the VCO frequency range, the patent skips lengthy calibration procedures. The calibration controller uses this quick measurement to directly calculate the required VCO control voltage adjustment, rushing through the calibration process efficiently before transitioning to normal PLL operation.
Data Source
AI summary
A phase lock loop (PLL) circuit includes a selection mode device before a phase detector and time-to-digital converter (TDC). In a first mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the reference clock signal. In a second mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the feedback clock signal. In a third mode, the selection mode device outputs the reference and feedback clock signals. The phase detector and TDC are configured to generate a signal: indicating the reference clock frequency in the first mode; indicating of the feedback clock frequency in the second mode; and indicating a phase/frequency difference between the feedback and reference clocks in the third mode. These signals are used to control a VCO clock signal.