PLL VCO Control Voltage Hold During Reference Clock Loss
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Solution Overview
Problem
Existing PLL systems experience prolonged re-locking times and frequency drift when a clock signal is lost, leading to instability in VCO operation, as conventional methods either disable the charge pump or rely on clamp circuits, resulting in significant voltage deviations from the lock voltage.
Innovation Solution
A semiconductor device with a control voltage maintenance circuit that uses a phase-frequency detector or voltage generator to maintain the VCO output frequency by operating off a master clock signal or alternative clock signals, ensuring the control voltage remains close to the locked state, thereby reducing drift and facilitating quicker re-locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the charge pump is disabled when clock signal is lost, then power consumption is reduced, but the control voltage drifts significantly from lock voltage causing prolonged re-locking time
Solution Approach 1:
The clamp circuit is pre-configured and activated immediately when clock signal is lost, preventing voltage drift before it occurs. The circuit maintains the control voltage at the locked state value through proactive intervention rather than reactive correction.
Solution Approach 2:
The clamp circuit acts as an intermediary element between the charge pump and loop filter, providing a stabilizing influence on the control voltage when the normal PLL operation is interrupted. It mediates the transition state to prevent harmful voltage excursions.
2Stability of the object's composition
If the clamp circuit is activated to hold the PLL at an operating point, then the control voltage is maintained between supply rails, but the voltage deviates significantly from the lock voltage extending re-locking time
Solution Approach 1:
The clamp circuit is designed to maintain the control voltage at the specific parameter value corresponding to the locked state, rather than merely holding it within a range. By targeting the precise lock voltage value, the circuit enables faster re-locking while maintaining stability.
3Adaptability or versatility
If the PLL remains active with charge pump driving the loop filter to a supply rail, then the circuit remains operational, but the control voltage drifts to extreme values causing potential damage and prolonged recovery
Solution Approach 1:
The clamp circuit provides preliminary protection against harmful voltage excursions by clamping the control voltage to safe levels before it can reach damaging values. This preventive measure protects the VCO and other sensitive components from reliability issues.
4Ease of manufacture
If conventional methods are used to handle clock loss, then the implementation is simple, but the VCO frequency stability is compromised during and after clock signal loss
Solution Approach 1:
The clamp circuit serves as a simple intermediary component that can be added to existing PLL designs without complex modifications. It provides frequency stability during clock loss events through a straightforward voltage clamping mechanism that maintains the control voltage at the locked state value.
Data Source
AI summary
A semiconductor device having a phase-locked loop (“PLL”) (100) drives a VCO (114) of the PLL circuit with a first control voltage (VCTRL) produced by a loop filter (112) when a first clock signal (clk_ref) is present. The VCO produces an output frequency while the PLL circuit is operating off the first clock signal. When the first clock signal is lost (ref_lost), a control voltage maintenance circuit (120) produces a second control voltage maintaining the VCO output frequency. In one device, the control voltage maintenance circuit includes a phase-frequency detector (104) that can operate off of either the clock reference signal or a master clock signal. In an alternative device, the control voltage maintenance circuit includes a voltage generator (334, 362) that produces a generated voltage that drives the loop filter when lock is lost.