PLL VCO Restart Circuit for Non-Oscillating Mode Recovery
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Solution Overview
Problem
Conventional phase-locked loops (PLLs) experience slow restart times due to reliance on external power down signals, which are not generated internally and cannot respond in real time to prevent non-oscillating modes.
Innovation Solution
Incorporating a detector circuit within the PLL that generates a pulse signal to restart the voltage-controlled oscillator (VCO) based on a control voltage threshold comparison, allowing for internal and rapid response to non-oscillating conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external power down signal is used to restart the PLL, then the PLL can be reset and restarted, but the response time is slow because the signal is external and not generated internally
Solution Approach 1:
The detector circuit is integrated within the PLL to autonomously monitor the control voltage and generate restart signals without external intervention. When the control voltage indicates non-oscillating mode, the detector circuit automatically triggers a pulse signal to restart the VCO, enabling the PLL to self-diagnose and self-restart, thereby eliminating the delay associated with external power down signals.
Solution Approach 2:
The detector circuit continuously monitors the control voltage as a feedback parameter and uses this information to determine when restart is needed. By feeding back the state of the control voltage to the restart mechanism, the system can respond immediately to non-oscillating conditions without waiting for external signals, thus reducing restart response time while maintaining reliability.
2Reliability
If multiple elements (charge pump, low-pass filter, VCO) are restarted using the power down signal, then the PLL can resume normal operation, but the restart process becomes slow due to the sequential restart of several elements
Solution Approach 1:
The invention extracts the essential restart function from the complex multi-element restart process. Instead of restarting the charge pump, low-pass filter, and VCO sequentially through the external power down signal, the detector circuit directly generates a pulse signal that targets and restarts only the VCO, which is the critical element for resuming oscillation. This selective approach maintains operational resumption while significantly reducing restart duration.
3Reliability
If the external power down signal is used to prevent non-oscillating mode, then the PLL can be restarted, but the signal cannot respond in real time because it is not generated by internal signals
Solution Approach 1:
The detector circuit implements continuous feedback monitoring of the control voltage to detect non-oscillating mode conditions in real time. When the control voltage exceeds a threshold indicating non-oscillating mode, the feedback mechanism immediately triggers a restart pulse, enabling real-time detection and response without the delay inherent in external power down signals.
Solution Approach 2:
The PLL system uses its own internal control voltage as the basis for detecting non-oscillating mode and generating restart signals. This self-service approach eliminates dependency on external signals, allowing the system to autonomously and rapidly respond to non-oscillating conditions using internally available information, thereby achieving both reliability and high response speed.
Data Source
AI summary
A phase-locked loop (PLL) and a method for controlling the PLL are provided. The PLL includes a phase detector, a charge pump, a voltage-controlled oscillator (VCO), a feedback frequency divider, and a detector circuit. The phase detector generates a direction signal according to a comparison between phases of a first clock signal and a second clock signal. The charge pump converts the direction signal into a control voltage. The VCO generates a third clock signal. The control voltage controls a frequency of the third clock signal. The feedback frequency divider divides the frequency of the third clock signal to generate the second clock signal. The detector circuit sends a pulse signal to restart the VCO when the control voltage conforms to a preset condition.