PLL Virtual Clock Holdover for Closed-Loop Phase Adjustment
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Solution Overview
Problem
Phase-locked loops (PLLs) face challenges in adjusting phase during holdover mode, where the loop is traditionally opened, preventing phase adjustments from being filtered and observed at the output, making it difficult to meet system requirements for phase/frequency changes.
Innovation Solution
Implementing a virtual clock signal as a reference clock signal, allowing for closed-loop holdover operation, where phase adjustments can be filtered and observed, using a virtual holdover clock signal generated internally within the PLL, which maintains loop closure and enables phase/frequency modulation even in holdover mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PLL loop is opened during holdover mode, then the system can continue operating without input reference signals, but phase adjustments cannot be filtered and observed at the output
Solution Approach 1:
A virtual clock signal is introduced as an intermediary reference during holdover mode. This virtual clock is generated internally by the PLL and used to maintain the feedback loop closure, allowing phase adjustments to be properly filtered and observed at the output while still operating in holdover condition
Solution Approach 2:
The system changes the reference clock parameter from an external physical clock to an internally generated virtual clock during holdover mode. This parameter change allows the loop to remain closed while adapting to the absence of external reference signals, preserving both holdover operation and phase adjustment functionality
2Reliability
If traditional holdover mode is used with open loop, then the system can operate during loss of signal, but phase adjustments on the M divider are not observed at the output
Solution Approach 1:
The virtual clock acts as a mediator that carries phase adjustment information through the holdover period. By using this internally generated reference, the phase adjustments made on the M divider are properly transmitted through the loop and observed at the output, preventing loss of phase control information
Solution Approach 2:
The virtual clock enables the feedback loop to remain closed during holdover mode. The feedback path continues to function properly with the virtual clock as reference, ensuring that phase adjustments are filtered by the loop and correctly reflected at the output signal
Data Source
AI summary
A PLL uses a virtual clock signal during holdover and/or startup to maintain a closed loop for the PLL and allow for phase/frequency adjustment of the PLL output through the feedback divider during holdover/startup when reference clock(s) supplied to the PLL are unavailable. The virtual clock signal is a series of digital values separated by a time period, where the digital values indicate transitions of the virtual clock signal and the time period corresponds to a period of the virtual clock signal. A selector circuit selects as a digital reference clock signal the virtual clock signal in a holdover or startup mode and another reference clock signal in normal operation.