PLL Frequency Demultiplication with Virtual Points for Stable CPU Scaling
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Solution Overview
Problem
Existing frequency demultiplication methods in PLLs for embedded systems suffer from insufficient available frequency points and large frequency differences, leading to instability and fluctuations when dynamically adjusting processor frequencies, especially under varying loads and high temperatures.
Innovation Solution
A frequency demultiplication adjustment method that introduces virtual frequency points by calculating equivalent frequencies within a predetermined sampling period, allowing the PLL to output a clock source signal corresponding to these points, thereby extending the frequency range and reducing frequency differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple PLLs are used to support a wide frequency range, then the frequency coverage is improved, but the system complexity and instability increase due to frequent switching between PLLs
Solution Approach 1:
The frequency range is segmented into multiple intervals, with each interval supported by a dedicated PLL. The patent divides the wide frequency range into several sub-ranges, assigning each PLL to support a specific sub-range. This segmentation allows the system to maintain stability within each sub-range while collectively covering the entire frequency spectrum, avoiding frequent PLL switching.
Solution Approach 2:
The patent introduces dynamic frequency demultiplication adjustment within each PLL's supported range. By dynamically adjusting the demultiplication factor based on load requirements, the system can fine-tune output frequencies without switching PLLs, thereby maintaining system stability while adapting to varying computational demands.
2Device complexity
If a single PLL operates at the highest frequency with external frequency demultiplication, then the device complexity is reduced, but the frequency adjustment precision deteriorates due to large frequency gaps
Solution Approach 1:
The patent applies partial demultiplication factors (e.g., 1/3, 1/5, 1/6) in addition to traditional integer demultiplication (1/2, 1/4, 1/8). This partial action approach fills the frequency gaps between standard demultiplication points, enabling finer frequency adjustment steps while still using a single PLL configuration, thus improving frequency precision without significantly increasing device complexity.
Solution Approach 2:
The patent changes the demultiplication parameter from fixed integer values to variable values including fractions. By allowing the demultiplication factor to vary between integer and fractional values, the system achieves continuous frequency adjustment capability, transforming the discrete frequency steps into a more continuous spectrum and thereby improving frequency adjustment precision.
Data Source
AI summary
A frequency demultiplication adjustment method of PLL comprises obtaining a plurality of corresponding frequency demultiplication frequency points according to a default frequency demultiplication value of a phase-locked loop; obtaining a load state of the processor within a predetermined sampling period, and obtaining a target frequency point of the processor by the processor frequency adjustor; determining a frequency range of a virtual frequency point to be added according to the position of the target frequency point; performing calculation within the frequency range to obtain equivalent frequencies corresponding to virtual frequency points; judging whether the frequency of the target frequency point is equal to the equivalent frequency corresponding to the virtual frequency points; if not, switching the processor frequency adjustor to the corresponding frequency demultiplication frequency point; and adjusting the frequency demultiplication value of the phase-locked loop which outputs a clock source signal corresponding to the virtual frequency points to the processor.