PLL Voltage Boosting for Frequency Overshoot Mitigation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Phase locked loops (PLLs) experience frequency overshoot when correcting phase or frequency changes, leading to increased supply voltage guard bands, which negatively impact system performance and limit the effectiveness of adaptive frequency scaling techniques.

Innovation Solution

An apparatus that temporarily boosts the supply voltage before a potential frequency overshoot event, allowing the PLL to lock quickly without long-term voltage guard bands, and then reduces the voltage back to its expected level, thereby avoiding unnecessary increases in minimum operating voltage (Vmin).

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the supply voltage is increased to compensate for frequency overshoot, then the PLL can maintain stable operation, but the minimum operating voltage (Vmin) increases and system performance decreases

Engineering Contradiction:
ImprovePLL stable operationVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by boosting the supply voltage to the PLL in advance before a frequency overshoot event occurs. This proactive voltage increase prepares the PLL to quickly acquire or re-acquire lock without experiencing significant frequency overshoot, thereby maintaining stable operation without requiring a permanently elevated Vmin that would degrade system performance.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If the PLL lock time is reduced for faster frequency transitions, then adaptive frequency scaling effectiveness improves, but frequency overshoot increases

Engineering Contradiction:
ImprovePLL lock timeVSAvoidfrequency overshoot
Core Design Contradiction:
Loss of timeVSObject-affected harmful factors

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the supply voltage parameter of the PLL based on operational conditions. When fast frequency transitions are required, the voltage is temporarily increased to enable quicker lock acquisition. This dynamic parameter adjustment allows the system to achieve fast lock times without incurring harmful frequency overshoot, as the voltage is optimized for each specific transition event rather than maintained at a fixed high level.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If supply voltage guard bands are increased to absorb frequency overshoot, then the compute subsystem can operate reliably, but the extent to which adaptive frequency scaling can be used is limited

Engineering Contradiction:
Improvecompute subsystem operationVSAvoidadaptive frequency scaling range
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies preliminary action by proactively boosting the supply voltage before frequency overshoot events occur, rather than relying on static guard bands. This approach allows the compute subsystem to operate reliably at lower Vmin levels because the voltage compensation is applied dynamically and temporarily only when needed, preserving the ability to use aggressive adaptive frequency scaling techniques across a wider range of operating conditions.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11847011B2Frequency overshoot and voltage droop mitigation apparatus and method
Publication Date: 2023.12.19 INTEL CORP
  • US11847011B2 patent drawing
  • US11847011B2 patent drawing
  • US11847011B2 patent drawing

AI summary

An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.