PLL Voltage Boosting for Frequency Overshoot Mitigation
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Solution Overview
Problem
Phase locked loops (PLLs) experience frequency overshoot and voltage droop, leading to increased supply voltage guard bands and reduced system performance, as existing mitigation techniques such as increasing guard bands or overdamping the PLL negatively impact lock/relock time and overall performance.
Innovation Solution
An apparatus that temporarily boosts the supply voltage and/or current before an event causing frequency overshoot, allowing the PLL to lock quickly without needing long-term voltage guard bands, and then reduces the voltage back to its expected level, thereby mitigating frequency overshoot without raising the minimum operating voltage (Vmin).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If supply voltage guard bands are increased to mitigate frequency overshoot, then frequency overshoot is reduced, but system performance decreases and minimum operating voltage (Vmin) increases
Solution Approach 1:
The patent applies preliminary action by temporarily boosting the supply voltage before a frequency change event occurs. This preemptive voltage boost prepares the PLL to handle the upcoming frequency transition without excessive overshoot, eliminating the need for permanent voltage guard bands and maintaining system performance.
Solution Approach 2:
The patent implements dynamics by making the supply voltage adjustable and time-dependent. The voltage is temporarily increased only during the brief period needed for frequency transitions, then returned to its normal level. This dynamic approach replaces static voltage guard bands with adaptive voltage control.
2Stability of the object's composition
If PLL is overdamped to reduce frequency overshoot, then frequency stability improves, but lock/relock time increases significantly
Solution Approach 1:
The patent uses preliminary action by providing a temporary voltage boost before frequency changes. This prepares the PLL in advance, allowing it to respond quickly to frequency transitions without requiring excessive damping that would slow down lock/relock times.
Solution Approach 2:
The patent applies preliminary anti-action by counteracting the potential frequency overshoot before it occurs through temporary voltage boosting. This prevents the need for strong damping mechanisms that would otherwise be required to control overshoot, thereby maintaining fast lock/relock times.
3Reliability
If supply voltage is temporarily boosted before frequency change events, then frequency overshoot is mitigated without increasing Vmin, but voltage control complexity increases
Solution Approach 1:
The patent implements preliminary action through automated voltage boosting triggered by frequency change detection. The system temporarily increases voltage just before frequency transitions occur, then automatically returns it to normal levels, achieving frequency overshoot mitigation without manual intervention or complex control logic.
4Reliability
If minimum operating voltage (Vmin) is increased to absorb frequency overshoot, then frequency overshoot impact is reduced, but power consumption increases and performance is limited
Solution Approach 1:
The patent applies dynamics by using temporary, time-limited voltage boosts instead of permanently increasing Vmin. The voltage is increased only for the brief duration needed to mitigate frequency overshoot during transitions, then returned to its normal level, thereby avoiding continuous extra power consumption while still providing frequency overshoot protection.
Data Source
AI summary
An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.