PLL Control Voltage Hold Circuit for Faster Wake-Up Lock
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Solution Overview
Problem
Conventional phase-locked loop (PLL) circuits exhibit high frequency lock time, leading to increased wake-up time in electronic devices, which is critical in time-sensitive applications and degrades performance, especially when transitioning from low power to run mode.
Innovation Solution
Incorporation of a capacitor and buffer amplifier in the PLL to store and buffer the control voltage, allowing for faster frequency lock when switching from low power to run mode, along with a charge compensation circuit to address voltage leakage, thereby reducing frequency lock time and wake-up time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the PLL is switched OFF during low power mode, then power consumption is reduced, but frequency lock time increases when switching back to run mode
Solution Approach 1:
The capacitor stores the control voltage before the PLL is switched off, maintaining the voltage level across the capacitor during low power mode. When the PLL is switched back on, the pre-stored voltage eliminates the need for slow charging through the low pass filter, enabling immediate frequency lock and reducing wake-up time while maintaining power savings.
2Stability of the object's composition
If the control voltage is continuously maintained through the low pass filter, then frequency stability is improved, but wake-up time increases due to slow charging
Solution Approach 1:
The capacitor acts as an intermediary energy storage element between the low pass filter and the VCO. It decouples the slow charging characteristic of the low pass filter from the VCO's frequency generation, allowing the VCO to immediately use the pre-stored voltage for frequency lock while the low pass filter continues to provide stable voltage regulation during normal operation.
3Device complexity
If the capacitor voltage is not compensated for leakage, then device complexity is reduced, but frequency locking accuracy deteriorates due to voltage drop
Solution Approach 1:
The charge compensation circuit monitors the capacitor voltage and automatically compensates for leakage current by replenishing the charge when the voltage drops below a threshold level. This feedback mechanism maintains accurate frequency locking without requiring complex control circuits, as the compensation is automatically triggered by voltage threshold detection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces frequency lock time and wake-up time of electronic devices, enhancing their performance and reliability in time-critical applications by enabling quicker transitions between power modes.
Implementation Method 1
a capacitor and a buffer amplifier. The capacitor samples and stores the control voltage generated by the low pass filter
Implementation Method 2
The buffer amplifier buffers the voltage across the capacitor and provides the buffered voltage to the low pass filter
Data Source
AI summary
A phase-locked loop (PLL) generates an oscillator signal based on an input reference signal. A voltage-to-current oscillator converts generates the oscillator signal based on a control. A charge pump circuit generates the charge pump current based on an error (feedback) signal. A low pass filter generates the control voltage based on the charge pump current. A capacitor is connected to an input terminal of the low pass filter that is charged to a voltage level of the control voltage by the low pass filter when the PLL is switched OFF. The voltage across the capacitor is buffered and fed back to the low pass filter when the PLL is switched ON, to reduce time taken by the VCO to generate the oscillator signal. The PLL is used in an electronic circuit to reduce the wake-up time of the electronic circuit.