PLL Control Voltage Restore for Fast Standby Exit Locking

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Solution Overview

Problem

Conventional semiconductor devices lose locking information and require a significant time to re-lock after exiting standby mode, impacting high-speed operation and power consumption.

Innovation Solution

A semiconductor device that stores the control voltage when locking is completed and uses this stored voltage to rapidly re-establish the locked state upon exiting standby mode, reducing the locking completion time and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If the control voltage is reset to supply voltage when entering standby mode, then power consumption is reduced and circuits are inactivated, but the locking information is lost and locking completion time increases when exiting standby mode

Engineering Contradiction:

Improvepower consumptionVSAvoidlocking completion time

Core Design Contradiction:

Use of energy by stationary objectVSLoss of time

Solution Approach 1:

The patent applies preliminary action by storing the control voltage at the V_CTR node before entering standby mode. The capacitor maintains this voltage level during standby, so when exiting standby mode, the locking information is already preserved and no time-consuming re-locking is needed. This resolves the contradiction by preparing the system in advance to avoid time loss later.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary element (capacitor) that mediates between the power consumption reduction goal and the locking information preservation requirement. The capacitor acts as a storage medium that holds the control voltage during standby mode, enabling both low power consumption and quick re-locking when exiting standby mode.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Loss of time

If the PLL circuits remain active to maintain locking information, then locking completion time is reduced, but power consumption increases

Engineering Contradiction:

Improvelocking completion timeVSAvoidpower consumption

Core Design Contradiction:

Loss of timeVSUse of energy by stationary object

Solution Approach 1:

The patent extracts the locking information (control voltage) from the active PLL circuits and stores it separately in the capacitor at the V_CTR node. This allows the PLL circuits to be inactivated during standby mode for low power consumption, while the extracted locking information remains preserved and can be quickly restored when needed.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the state parameter of the control voltage from being dynamically maintained by active circuits to being statically stored as an electrical charge in a capacitor. This parameter change enables the system to maintain locking information without continuous power consumption, resolving the contradiction between speed and power usage.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8653866B2Semiconductor device and operating method thereof

Publication Date: 2014.02.18 MIMIRIP LLC

AI summary

A semiconductor device includes a control voltage generating block configured to generate a control voltage corresponding to a phase difference between a reference clock signal and an internal clock signal, a control voltage restoring block configured to store the control voltage as a restoring voltage when entering into a low power mode and to supply the restoring voltage to a control voltage node when exiting from the low power mode, and an internal clock signal generating block configured to generate the internal clock signal corresponding to a voltage level of the control voltage.