Phase-Locked Loop Using Weighted Reference Clocks for Lower Phase Noise
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Solution Overview
Problem
Existing phase-locked loops face challenges in balancing in-band and out-of-band phase noise while minimizing power consumption, as reducing in-band phase noise requires higher power consumption, leading to an interdependence between phase noise and power consumption.
Innovation Solution
A phase-locked loop design incorporating multiple synchronized reference clock signals, a phase discrimination unit, and a weighting unit to determine and weight error signals, achieving phase domain averaging to reduce the influence of in-band phase noise on power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the bandwidth of the phase-locked loop is reduced to minimize in-band phase noise, then the in-band phase noise is reduced, but the out-of-band phase noise becomes dominant requiring a lower noise VCO which increases power consumption
Solution Approach 1:
The patent segments the reference clock signal into multiple frequency components (first reference clock signal and second reference clock signal with different frequencies). By processing these segmented frequency components separately through parallel PLL channels and then combining them, the system achieves noise reduction without requiring excessive power consumption in a single VCO.
Solution Approach 2:
The patent merges multiple reference clock signals with different frequencies into a composite reference clock signal. This combining approach allows the system to leverage the advantages of multiple frequency components, achieving reduced phase noise while distributing power consumption across multiple lower-power VCOs operating at different frequencies.
2Object-affected harmful factors
If multiple reference clock signals with different frequencies are used to reduce phase noise, then phase noise is reduced, but the device complexity increases
Solution Approach 1:
The patent implements a multi-functional reference clock unit that can generate multiple reference clock signals with different frequencies from the same hardware structure. This universal design allows the system to achieve phase noise reduction through frequency diversity while avoiding the need for separate clock generation circuits for each frequency, thereby limiting the increase in device complexity.
3Object-affected harmful factors
If the VCO power consumption is increased to achieve lower out-of-band phase noise, then the out-of-band phase noise is reduced, but the overall power consumption increases
Solution Approach 1:
The patent employs dynamic frequency switching between multiple reference clock signals with different frequencies. By dynamically selecting and switching between different frequency components based on operational requirements, the system can optimize the balance between phase noise performance and power consumption, avoiding the need to continuously operate a single high-power VCO at maximum capability.
Data Source
AI summary
A phase-locked loop, a signal processing device and a signal processing method. In the phase-locked loop, a reference clock unit outputs two or more frequency-adjustable synchronous reference clock signals to a phase discrimination unit; a feedback unit performs frequency division processing on an output voltage signal, which is output by the phase-locked loop within a first period, so as to obtain a feedback signal; the phase discrimination unit determines a corresponding error signal for each reference clock signal according to the phase difference between each reference clock signal and the feedback signal; a weighting unit performs weighting calculation on the determined error signals, so as to obtain a weighted error signal; and a correction unit is configured to correct, according to the weighted error signal, an output voltage signal, which is output by the phase-locked loop within a second period.