Injection-Locked PLL Window Timing for Stable Oscillation
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Solution Overview
Problem
Injection-locked PLL circuits face issues such as glitches, harmonic oscillations, and instability due to PVT variations, which affect the window width and lead to malfunctions, especially under frequency variations or noise disturbances, making them unsuitable for applications requiring high reliability.
Innovation Solution
The proposed solution involves a PLL circuit with a variable frequency oscillator, a feedback circuit, and a window generator that allows the injection of a reference clock edge during a negated window period, independent of the reference clock, ensuring stable oscillation and preventing glitches and harmonic oscillations by adjusting the window timing to include the injection edge within its assertion period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the window width is adjusted to include the injection edge timing, then the PLL circuit achieves stable oscillation and prevents glitches, but the circuit complexity increases due to additional timing control mechanisms
Solution Approach 1:
The patent implements feedback control by monitoring the injection edge timing and adjusting the window signal assertion period accordingly. The feedback circuit detects when the injection edge occurs and dynamically modifies the window width to ensure it encompasses the injection edge, thereby achieving stable oscillation while automatically adapting to timing variations without requiring complex manual calibration
Solution Approach 2:
The window width is made dynamic rather than fixed. The assertion period of the window signal is automatically adjusted based on the actual injection edge timing, allowing the system to adapt to PVT variations and frequency changes. This dynamic adjustment mechanism prevents glitches and harmonic oscillations while maintaining reasonable circuit complexity through automated control
2Area of stationary object
If the injection-locked PLL circuit is used to reduce chip area, then the chip size becomes smaller compared to analog PLL, but the circuit becomes susceptible to PVT variations causing glitches and harmonic oscillations
Solution Approach 1:
The patent changes the timing parameters of the window signal dynamically. By adjusting the assertion period of the window signal based on injection edge timing, the system adapts to PVT variations and frequency changes. This parameter adjustment ensures that the injection edge is always captured within the window period, preventing glitches and harmonic oscillations while maintaining the compact digital circuit architecture
Solution Approach 2:
The system performs preliminary timing analysis to determine when the injection edge will occur, then pre-adjusts the window assertion period to ensure it will encompass the injection edge. This preliminary action prevents the occurrence of glitches and harmonic oscillations before they can happen, enhancing reliability while maintaining the compact digital circuit design
3Adaptability or versatility
If the window signal assertion period is extended to cover frequency variations, then the circuit becomes more robust against frequency changes, but the injection timing precision decreases
Solution Approach 1:
The system uses feedback control to dynamically adjust the window assertion period based on detected injection edge timing. Rather than using a fixed extended window that would reduce precision, the feedback mechanism ensures the window is precisely sized to encompass the injection edge, maintaining both robustness against frequency variations and injection timing precision through adaptive control
Data Source
AI summary
Disclosed here is a PLL circuit that is an injection-locked PLL circuit. The PLL circuit includes a variable frequency oscillator configured in such a manner that a ring oscillator is formed during a period in which a window signal is negated and an injection edge based on a reference clock is allowed to be injected during a period in which the window signal is asserted, a feedback circuit that controls the variable frequency oscillator in such a manner that an oscillation frequency of the variable frequency oscillator gets closer to a target frequency according to the reference clock, and a window generator that receives an internal clock of the variable frequency oscillator and cuts out one pulse to generate the window signal.