PLP-Assisted Storage Memory Idle Power and Data Retention

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Solution Overview

Problem

Semiconductor storage devices face challenges in balancing power consumption and performance, particularly in idle states, which affect the operating costs and efficiency of storage servers.

Innovation Solution

Incorporating a power loss protection (PLP) IC and auxiliary power supply to generate internal power for self-refresh operations in volatile memory devices, reducing external power usage during idle states by transitioning to an idle mode and performing background flush operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the storage device uses external power supply continuously, then the volatile memory device can maintain data, but power consumption increases during idle states

Engineering Contradiction:
Improvedata retentionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The PLP IC charges the internal power supply voltage in advance during normal operation before power loss occurs. This preliminary charging allows the volatile memory device to maintain data using stored internal power during idle states without continuous external power supply, thus reducing power consumption while ensuring data retention reliability.

Inventive Principle:
Principle #10Preliminary action

2Use of energy by moving object

If the storage device enters idle state with reduced power, then power consumption decreases, but data in volatile memory may be lost

Engineering Contradiction:
Improvepower consumptionVSAvoiddata retention
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The PLP IC acts as an intermediary power management component that switches between external power supply and internal power supply voltage. During idle states, it seamlessly transitions to internal power from the auxiliary power supply, ensuring continuous power delivery to the volatile memory device without data loss, while enabling the storage device to reduce external power consumption.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If background flush operation is performed frequently, then data accuracy improves, but processing time increases

Engineering Contradiction:
Improvedata accuracyVSAvoidprocessing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The storage controller performs background flush operations periodically based on time intervals rather than continuously. This periodic execution ensures data is flushed from volatile to non-volatile memory at appropriate intervals, maintaining data accuracy while avoiding excessive processing time overhead compared to continuous flushing.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20260044265A1Storage device and data center including the same
Publication Date: 2026.02.12 SAMSUNG ELECTRONICS CO LTD
  • US20260044265A1 patent drawing
  • US20260044265A1 patent drawing
  • US20260044265A1 patent drawing

AI summary

A storage device includes at least one nonvolatile memory device, a volatile memory device, a storage controller, an auxiliary power supply and a power loss protection (PLP) integrated circuit (IC). The PLP IC provides one of an internal power supply voltage or an external power supply voltage. The storage controller enters the storage device into an idle state in response to the storage controller not receiving a new request from a host during a first time interval and performs a background flush operation to move a first data temporarily stored in the volatile memory device to the nonvolatile memory device in response to a second time interval elapsing from the storage device entering into the idle state. In the idle state, the PLP IC provides the internal power supply voltage to the volatile memory device and the volatile memory device performs a self-refresh operation using the internal power supply voltage.