Circuit Structure Layout for PLP Warpage Suppression
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Solution Overview
Problem
Panel level package (PLP) carriers and circuit structures often suffer from warpage, which can lead to adverse effects on subsequent manufacturing processes, such as solder ball mounting and electronic component bonding, resulting in reduced yield and reliability.
Innovation Solution
A manufacturing method for electronic devices that involves providing a carrier with alternately disposed conductive and insulating layers, electrically connecting adjacent conductive layers through holes in the insulating layers, and incorporating a structural unit with a specific thermal expansion coefficient ratio to the conductive layers, which alleviates warpage by opposing the warping direction of the structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If carriers and circuit structures are used in panel level package, then electronic device assembly is enabled, but warpage occurs affecting manufacturing precision
Solution Approach 1:
The patent applies parameter changes by carefully selecting materials with specific thermal expansion coefficients for different layers. The insulating layer is designed with a thermal expansion coefficient higher than the conductive layer, creating a controlled differential expansion that compensates for warpage during thermal processing. This parameter optimization resolves the contradiction between assembly capability and warpage control.
Solution Approach 2:
The patent uses composite material structure with alternately disposed conductive layers and insulating layers having different thermal expansion properties. This composite design creates internal stress balance that counteracts warpage, enabling both easy assembly and precise manufacturing control simultaneously.
2Device complexity
If warpage is not controlled, then manufacturing process simplicity is maintained, but yield and reliability decrease
Solution Approach 1:
By optimizing the thermal expansion coefficient ratio between insulating and conductive layers within specific ranges (1.05-1.30 for first embodiment, 0.95-1.20 for second embodiment), the patent achieves automatic warpage compensation during normal manufacturing processes without adding complex control steps, thus maintaining process simplicity while improving yield and reliability.
3Adaptability or versatility
If thermal expansion coefficients are mismatched, then material selection flexibility is high, but warpage increases reducing reliability
Solution Approach 1:
The patent establishes specific parameter ranges for thermal expansion coefficients (first insulating layer: 10-50×10^-6/K, second insulating layer: 15-55×10^-6/K in first embodiment; first insulating layer: 8-45×10^-6/K, second insulating layer: 12-50×10^-6/K in second embodiment) that balance material selection flexibility with warpage control, allowing various material choices while ensuring reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively suppresses warpage, improving the yield and reliability of electronic devices by ensuring proper alignment and bonding during manufacturing processes.
Implementation Method 1
The structural unit has a first thermal expansion coefficient, one of the plurality of conductive layers of the circuit structure has a second thermal expansion coefficient, and a ratio of the first thermal expansion coefficient to the second thermal expansion coefficient is greater than or equal to 1.2 and less than or equal to 2
Data Source
AI summary
An electronic device and a manufacturing method thereof are provided in the present disclosure. The electronic device includes a circuit structure, a plurality of electronic components and a structural unit. The circuit structure includes a plurality of conductive layers and at least one insulating layer. The plurality of conductive layers are electrically interconnected via a plurality of through holes in the at least one insulating layer. The plurality of electronic components are electrically connected to the circuit structure and are overlapped with the circuit structure. The structural unit is disposed adjacent to the plurality of electronic components. In a top view of the electronic device, at least a portion of the structural unit is disposed between adjacent two of the electronic components.