Pseudo-LRU Toggling Logic for Cache Allocation Conflicts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In cache memories, when two units (load and store units) miss and attempt to allocate entries in the same set, existing pseudo-LRU (PLRU) schemes fail to prevent allocation conflicts, degrade performance, and introduce timing issues, as they often allocate the same way or require slow updates.
Innovation Solution
A PLRU vector is generated using a tree of bits, with toggling logic that creates a new vector by inverting bits at specific levels to allocate different entries for concurrent requests, ensuring efficient and quick allocation without immediate conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLRU schemes are used for cache allocation, then the allocation logic is simple, but allocation conflicts occur when two units miss and attempt to allocate entries in the same set simultaneously
Solution Approach 1:
The PLRU vector is segmented into multiple levels (first level, second level, third level) corresponding to different groups of ways. Each level handles allocation for a specific group, allowing concurrent allocations in different groups without conflict while maintaining simple per-level logic.
Solution Approach 2:
The patent introduces a hierarchical dimension to the PLRU structure by organizing ways into groups and creating multiple levels of PLRU vectors. This dimensional organization allows simultaneous allocations in different groups while preventing conflicts within the same group, resolving the contradiction between simplicity and conflict prevention.
2Reliability
If the PLRU vector is updated after allocation to prevent future conflicts, then allocation conflict prevention improves, but the timing and update logic become more complex
Solution Approach 1:
The PLRU vector is updated immediately upon detecting a concurrent allocation request, before the allocation is fully completed. This preliminary update ensures that the next allocation in the same group will select a different way, preventing future conflicts while maintaining timing efficiency.
Solution Approach 2:
The system uses feedback from the allocation request detection to trigger PLRU vector updates. When concurrent requests are detected, the PLRU vector is updated based on this feedback signal, ensuring that future allocations are fair without requiring complex timing control.
3Productivity
If the same way is allocated to both units during concurrent misses, then allocation speed is fast, but one unit immediately kicks out the other degrading performance
Solution Approach 1:
The patent applies different allocation behaviors to different groups of ways based on local conditions. Each group of ways has its own PLRU level that independently manages allocations, allowing fast local allocation within each group while ensuring that concurrent allocations in the same group select different ways, maintaining performance.
Data Source
AI summary
An apparatus for allocating entries in a set associative cache memory includes an array that provides a first pseudo-least-recently-used (PLRU) vector in response to a first allocation request from a first functional unit. The first PLRU vector specifies a first entry from a set of the cache memory specified by the first allocation request. The first vector is a tree of bits comprising a plurality of levels. Toggling logic receives the first vector and toggles predetermined bits thereof to generate a second PLRU vector in response to a second allocation request from a second functional unit generated concurrently with the first allocation request and specifying the same set of the cache memory specified by the first allocation request. The second vector specifies a second entry different from the first entry from the same set. The predetermined bits comprise bits of a predetermined one of the levels of the tree.