Plug-Level Power Rails Under Bottom Metal Layer
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Solution Overview
Problem
In the formation of integrated circuits, the wide power rails and the need for numerous jogs to connect them to standard cells lead to process issues and inefficient use of chip area for power routing, as existing power routing schemes require significant resources that could be used for signal lines.
Innovation Solution
A novel layout scheme where plug-level power rails are used, extending to three boundaries of each standard cell and connected via vias to overlying power rails in the same metal layer, allowing for shared power supply and reducing the need for jogs, thus optimizing chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional power routing schemes are used with wide power rails and numerous jogs to connect to standard cells, then power delivery is achieved, but chip area is significantly consumed and process issues arise
Solution Approach 1:
The patent moves power rails from the planar metal layer to a vertical dimension by forming them in trenches within the semiconductor substrate. This dimensional transition allows power delivery without consuming valuable planar chip area, as the power rails now occupy the vertical subsurface space rather than competing for horizontal routing resources.
Solution Approach 2:
The power rails are nested within the semiconductor substrate structure itself, specifically formed in trenches that are integrated into the substrate. This nesting approach embeds the power delivery infrastructure within the existing device structure, eliminating the need for separate planar power rail formations and reducing overall chip area consumption.
2Reliability
If wide power rails are used in the same metal layer as signal lines, then power delivery is ensured, but routing resources for signal lines are significantly reduced
Solution Approach 1:
By transitioning power rails from the horizontal metal layer to a vertical trench structure within the substrate, the patent creates spatial separation between power delivery paths and signal routing paths. This dimensional separation allows both power and signal lines to coexist without competing for the same planar routing resources, thereby maintaining full routing adaptability for signals while ensuring reliable power delivery.
3Reliability
If numerous jogs are formed to connect power rails to standard cells, then power connection is achieved, but process complexity increases
Solution Approach 1:
The patent extracts the power rail formation from the complex planar metal layer structure and relocates it to simple trench structures within the substrate. This extraction eliminates the need for numerous jogs and complex metal layer manipulations, as power connections are achieved through straightforward vertical vias accessing the trench-based power rails, thereby significantly reducing process complexity.
Data Source
AI summary
A circuit includes a semiconductor substrate; a bottom metal layer over the semiconductor substrate, wherein no additional metal layer is between the semiconductor substrate and the bottom metal layer; and a cell including a plug-level power rail under the bottom metal layer.