Plug-Protrusion Interconnect Structure for Low-k Wiring Reliability
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Solution Overview
Problem
Existing semiconductor manufacturing methods face challenges in reducing wiring resistance and inter-wiring capacitance while ensuring reliable connections between plugs and wirings, particularly with the use of copper wiring and low dielectric constant films, leading to signal delay and reduced reliability.
Innovation Solution
A method involving the formation of a first plug with its upper surface higher than the interlayer insulating film, followed by a second interlayer insulating film with a lower dielectric constant, and a buried wiring connected to the plug, where the wiring's lower surface is lower than the plug's upper surface, ensuring reduced inter-wiring capacitance and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If copper wiring is used to reduce wiring resistance, then wiring resistance is reduced, but manufacturing complexity increases due to the need for specialized barrier layers and deposition processes
Solution Approach 1:
The patent segments the wiring structure into multiple functional layers: a barrier layer (e.g., tantalum nitride or tungsten nitride) deposited first to prevent copper diffusion, followed by a copper layer deposited via electroplating or CVD. This segmentation allows each layer to perform its specific function independently, enabling copper wiring to reduce resistance while the barrier layer manages the manufacturing complexity by preventing contamination and enabling selective deposition processes.
2Loss of energy
If low dielectric constant films are used to reduce inter-wiring capacitance, then inter-wiring capacitance is reduced, but film deposition complexity and process control difficulty increase
Solution Approach 1:
The patent employs composite interlayer insulating films combining multiple materials with different dielectric constants. For example, a first interlayer insulating film (such as silicon oxide or silicon oxynitride) is deposited to provide mechanical strength and adhesion, followed by a second interlayer insulating film (such as silicon carbon oxide or porous low-k material) with lower dielectric constant to reduce inter-wiring capacitance. This composite structure allows the system to achieve low capacitance while managing deposition complexity through standardized multi-layer fabrication processes.
3Reliability
If the plug upper surface is made higher than the interlayer insulating film surface, then connection reliability is improved, but the risk of wiring short circuit and signal interference increases
Solution Approach 1:
The patent applies local quality by creating a recessed wiring structure where the wiring is positioned lower than the plug upper surface. Specifically, the wiring is formed in a trench or recess within the interlayer insulating film, such that the wiring upper surface is lower than the plug upper surface. This local geometric modification ensures reliable electrical connection between the plug and wiring while preventing short circuits and reducing signal interference, as the recessed wiring maintains proper electrical isolation from adjacent structures.
4Reliability
If the wiring is formed as a buried wiring with lower surface lower than plug upper surface, then short circuit prevention is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements preliminary action by forming the wiring trench or recess in the interlayer insulating film before depositing the wiring material. This pre-formed structural guide ensures that the wiring is automatically positioned at the correct depth and location, with the wiring upper surface lower than the plug upper surface. The preliminary trench formation simplifies subsequent wiring deposition and ensures precise depth control, reducing the manufacturing precision burden on later steps while maintaining reliable short circuit prevention.
Data Source
AI summary
An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.