Power-Mode-Aware Clock Tree Buffer Delay Control
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Solution Overview
Problem
Traditional clock trees in integrated circuits face challenges in maintaining consistent clock skew across different power modes, leading to increased clock latency and skew between function modules, which is not adequately addressed by existing asynchronous designs, adjustable delay buffers, or delay locked loops due to their complexity and resource requirements.
Innovation Solution
The proposed solution involves a clock tree design with first and second sub-clock trees and power-mode-aware (PMA) buffers, where PMA buffers are used to dynamically adjust delay times based on power mode information, minimizing clock skew by optimizing delay times for different power voltages across function modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional clock trees are used in integrated circuits, then the clock distribution is simple, but the clock skew between function modules increases significantly across different power modes
Solution Approach 1:
The patent applies dynamics by making the clock buffer delay adjustable based on power mode. The clock tree transitions from a static structure to a dynamic one where delay elements can be reconfigured. Specifically, the patent uses adjustable delay buffers that can modify their delay characteristics according to the operating power mode, allowing the clock distribution network to adapt its timing properties dynamically rather than being fixed for a single operating condition
Solution Approach 2:
The patent changes the delay parameter of clock buffers based on power mode. By detecting the current power mode and adjusting the delay values of clock buffers accordingly, the system optimizes clock skew for each specific operating condition. This involves modifying electrical parameters (delay time) of clock distribution elements in response to changing power voltage levels across different function modules
2Manufacturing precision
If asynchronous designs are used to address clock skew, then clock skew between power modes can be managed, but the system complexity and resource requirements increase
Solution Approach 1:
The patent applies self-service by enabling the clock distribution network to automatically adjust its own timing characteristics without external intervention. The system includes power mode detection circuitry that autonomously identifies the current power mode and triggers appropriate delay adjustments in the clock buffers. This self-adjusting mechanism eliminates the need for complex external control systems or manual reconfiguration, allowing the clock tree to service its own timing requirements adaptively
3Manufacturing precision
If adjustable delay buffers are used to optimize clock skew, then clock timing precision improves, but the number of buffers and chip area consumption increase
Solution Approach 1:
The patent applies universality by designing clock buffers that can serve multiple functions: they operate as standard clock buffers in normal mode and as adjustable delay elements when power mode adaptation is required. This multi-functionality allows the same hardware structure to perform both basic clock distribution and dynamic skew compensation, eliminating the need for separate dedicated delay adjustment circuits and reducing overall chip area consumption
Data Source
AI summary
A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.