PMA Overclocking With Phase Control for Low-Latency Receivers
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Solution Overview
Problem
Current communication systems, particularly in high-frequency trading, face significant latency due to high transceiver latency, with no efforts made to improve the physical medium attachment (PMA) portion, which accounts for approximately 50% of overall latency.
Innovation Solution
Overclocking the physical medium attachment (PMA) while controlling jitter tolerances and ensuring run-length performance, either with or without overclocking the physical coding sublayer (PCS), using a device comprising a PMA, PCS, phase detector, oscillator, and phase locked loop (PLL) to increase data speed and adjust phases, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the PMA is overclocked to reduce latency, then the speed of data transmission is improved, but jitter tolerances and run-length performance may deteriorate
Solution Approach 1:
The system dynamically adjusts the clock frequency of the PMA layer independently from other layers. The clocking mechanism is made adaptable by allowing frequency changes based on latency requirements, while the phase detector and phase-locked loop continuously monitor and adjust to maintain signal integrity and timing accuracy despite the increased speed
Solution Approach 2:
The invention changes the operating parameter (clock frequency) of the PMA layer specifically, overclocking it to reduce latency. This parameter change is isolated to the PMA layer while other layers maintain their standard operating frequencies, allowing speed improvement without compromising overall system reliability
2Loss of time
If the PMA is overclocked to reduce latency, then the overall latency is reduced, but the device complexity increases due to additional phase detection and clock adjustment mechanisms
Solution Approach 1:
The transceiver is segmented into distinct layers (PMA, PCS, etc.) with independent clocking mechanisms. The phase detector and phase-locked loop are specifically applied to the PMA layer to handle the overclocking requirements, isolating the complexity to only the portion of the system that needs it, rather than complicating the entire transceiver architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach can reduce overall latency by approximately 25% or more, improving communication efficiency in latency-sensitive applications like high-frequency trading by directly addressing PMA latency without affecting the PCS.
Implementation Method 1
The phase detector receives another data from the PCS wherein the another data is based on the received data at the second speed or the phase detector is configured to receive the data at the second speed directly from the PMA. The phase detector adjusts a phase based on bit transitions.
Implementation Method 2
the device further includes a phase locked loop (PLL) coupled to the oscillator. The PLL is configured to increase a frequency of the adjusted clock.
Implementation Method 3
The oscillator is coupled to the phase detector and generates a reference clock signal wherein a phase of the reference clock is adjusted by the phase detector.
Data Source
AI summary
A device includes a physical medium attachment (PMA), a physical coding sublayer (PCS), a phase detector, and an oscillator. The PMA receives data at a first speed and overclocks the received data to a second speed, wherein the second speed is higher than the first speed. The PCS receives the data at the second speed. The phase detector receives another data from the PCS wherein the another data is based on the received data at the second speed or the phase detector is configured to receive the data at the second speed directly from the PMA. The phase detector adjusts a phase based on bit transitions. The oscillator is coupled to the phase detector and generates a reference clock signal wherein a phase of the reference clock is adjusted by the phase detector. The oscillator clocks the PMA based on the adjusted clock.