Non-Volatile CAM Cells Using Programmable Metallization
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Solution Overview
Problem
Conventional content addressable memories (CAMs) are expensive and have large transistor counts, which complicates their design and operation, especially in binary CAM (BCAM) and ternary CAM (TCAM) applications.
Innovation Solution
The use of programmable metallization cells (PMCs) to create non-volatile CAM cells with reduced transistor counts, where PMCs are coupled with access transistors and match indication transistors to simplify the cell structure and enable efficient comparison operations, allowing for the formation of both BCAM and TCAM cells with fewer transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CAM cells are used, then reliable data storage and comparison functions are achieved, but transistor counts become large and device complexity increases
Solution Approach 1:
The patent merges the storage element and comparison logic into a single integrated CAM cell unit. Each cell contains a storage node with data bits, a reference node with reference bits, and shared access transistors that control both nodes simultaneously. This merging eliminates the need for separate storage and comparison circuits, reducing overall transistor count while maintaining reliable data storage and comparison functions.
Solution Approach 2:
The access transistors serve multiple functions: they control the storage node for data writing, control the reference node for data reading, and enable comparison operations. The match line serves both as a comparison output and as a control signal for subsequent operations. This multi-functionality reduces the total number of components needed in the CAM cell architecture.
2Adaptability or versatility
If conventional CAM cells are used, then complete comparison functionality is achieved, but cell structure becomes complex and manufacturing cost increases
Solution Approach 1:
The CAM cell is segmented into distinct functional regions: a storage node containing data bits, a reference node containing reference bits, a match line for comparison output, and access transistors for control. This segmentation allows each region to be optimized independently and simplifies the manufacturing process by enabling modular fabrication and testing of individual cell components before assembly into the full CAM array.
3Device complexity
If reduced transistor count is achieved, then device complexity decreases, but ensuring reliable match indication becomes more difficult
Solution Approach 1:
The match line provides feedback about the comparison result between storage and reference nodes back to the access transistors and control logic. When bits match, the match line maintains a specific state that enables subsequent operations; when bits mismatch, the match line changes state to disable operations. This feedback mechanism ensures reliable match indication accuracy despite the reduced transistor count in the cell structure.
Data Source
AI summary
Methods and circuits for CAM cells using PMCs are disclosed herein. In one embodiment, a BCAM cell can include: (i) a first PMC coupled to a first access transistor and a bit node, where the first access transistor is coupled to a true bit line; (ii) a second PMC cell coupled to a second access transistor and the bit node, where the second access transistor is coupled to a complement bit line, and the first and second access transistors are controllable by a word line; (iii) a program enable transistor coupled to the bit node, and configured to couple a program control voltage to the bit node when enabled; and (iv) a match indication transistor configured to discharge a match line in response to states of the true and complement bit lines relative to the bit node.