Programmable Metallization Cell Programming and Erase Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices using programmable metallization cells (PMCs) face challenges in achieving symmetric program and erase operations without the need for charge pumps, and in efficiently verifying the state of PMCs during erase and program operations.
Innovation Solution
The integration of programmable metallization cells (PMCs) with ion conducting materials and metal electrodes, where an active metal anode dissolves into the ion conductor and an inert cathode does not, allowing for compact memory arrays with shared source nodes and controlled impedance paths, enabling symmetric program and erase operations without external charge pumps, and incorporating erase and verify circuits to confirm PMC states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If charge pumps are used to achieve symmetric program and erase operations in PMC memory devices, then programming capability is improved, but device complexity increases
Solution Approach 1:
The patent removes the charge pump circuitry from the memory device architecture. Instead of using charge pumps to generate high voltage for programming, the invention uses the existing power supply rails (VDD and VSS) directly to achieve symmetric program and erase operations by appropriately selecting which electrode to connect to VDD and which to VSS.
Solution Approach 2:
The patent makes the power supply system multi-functional by using the same VDD and VSS rails for both programming and erasing operations, as well as for reading. The access devices and PMC electrodes are configured to work with these universal power rails, eliminating the need for separate high-voltage charge pump circuits.
2Ease of operation
If separate source nodes are used for each PMC in the memory array, then programming control is improved, but memory array size increases
Solution Approach 1:
The patent merges multiple source nodes into shared source nodes. Multiple PMCs in the memory array share common source nodes, which are selectively connected to VDD or VSS through access devices. This sharing reduces the total number of source nodes required while maintaining the ability to control programming operations through the access devices.
3Reliability
If verification circuits are added to confirm PMC states during erase and program operations, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements self-verification where the existing read circuitry and power supply system are used to verify PMC states during programming and erasing operations. The system uses the same access devices and power rails to both program/erase and to verify the resulting state, eliminating the need for separate dedicated verification circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient, symmetric program and erase operations within the power supply range, reducing complexity and power consumption, and ensures accurate verification of PMC states, enhancing memory device performance and endurance.
Implementation Method 1
an active metal anode dissolves into the ion conductor
Implementation Method 2
ion conducting material
Data Source
AI summary
An integrated circuit can include a plurality of programmable metallization cells (PMCs) in a memory array, each PMC comprising an ion conducting material, an active metal dissolvable in the ion conducting material, and two electrodes, a first electrode of at least one PMC being coupled to a program node; and a plurality of program and verify circuits, each including a current source section to enable at least one current path between the program node and a power supply node in a program and verify operation, and a verify signal generator circuit comprising at least a first comparator having a first input coupled to the program node, a second input coupled to receive a first reference voltage, and a comparator output to provide a verify signal that indicates a program operation is complete.