Power Management Controller Synchronous Reset for IC Voltage Domains
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits (ICs) face performance degradation due to asynchronous resetting of multiple voltage domains, which can lead to meta-stable states and malfunctioning, caused by varying propagation delays and on-chip variations in power management controllers (PMCs).
Innovation Solution
A power management controller (PMC) is designed to generate synchronous reset signals for multiple voltage domains by using voltage regulators, detectors, and a voltage controller, which determine voltage levels and external power-on-reset signals to produce master reset signals, ensuring simultaneous resetting of voltage domains during power-up and operational modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple voltage domains are reset independently using separate reset signals, then each voltage domain can be reset according to its own timing, but the voltage domains may be reset asynchronously causing meta-stable states and IC malfunction
Solution Approach 1:
The patent combines multiple independent reset signals into a single master reset signal that controls all voltage domains simultaneously. The reset controller receives individual reset requests from each voltage domain and generates one synchronized master reset signal, ensuring all domains reset together to prevent meta-stable states while still allowing each domain to independently request resetting when needed.
2Reliability
If a single master reset signal is used for all voltage domains, then synchronous resetting is achieved, but the system lacks flexibility to reset individual domains independently
Solution Approach 1:
The reset controller dynamically adjusts its behavior based on incoming reset requests. When multiple domains need resetting, it generates a master reset signal for synchronous resetting. The system can also handle different reset timing requirements by selectively generating master reset signals based on which domains require resetting, providing both synchronous operation and individual domain control flexibility.
3Loss of time
If voltage domains are reset asynchronously due to propagation delays, then individual domain reset timing is maintained, but IC performance degrades due to meta-stable states
Solution Approach 1:
The reset controller acts as an intermediary between individual voltage domains and the reset mechanism. It receives reset requests from various domains, synchronizes them, and generates a single master reset signal that ensures all domains reset simultaneously. This intermediary function eliminates the harmful effects of propagation delays and asynchronous resetting while maintaining the ability to reset individual domains when needed.
Data Source
AI summary
A power management controller (PMC) for resetting various voltage domains of an integrated circuit (IC) generates and transmits first and second voltage domain input signals to first and second voltage domains, respectively, and generates corresponding reset signals for resetting the first and second voltage domains. The PMC generates a first master reset signal indicative of resetting the first and second voltage domains when the first and second voltage domains are booting. The PMC generates a second master reset signal indicative of resetting the first and second voltage domains when the IC is in a functional mode. The PMC determines whether the first and second voltage domains are non-functional and if at least one is non-functional, then the PMC masks a respective one of the first and second reset signals.