DRAM Cache for Persistent Memory Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Cloud computing platforms face inefficiencies due to the slow speed of bulk byte-addressable persistent memory (PMEM) compared to dynamic random-access memory (DRAM), which conventional systems have not been able to address effectively, as PMEM is typically exposed as a storage device rather than memory, and previous solutions for operating system non-uniform memory access (NUMA) mechanisms are insufficient.
Innovation Solution
A framework is provided to allow guest operating systems to directly use PMEM by presenting it as a slower DRAM through BIOS and OS reporting mechanisms, implementing a caching mechanism to transfer frequently used memory pages from PMEM to DRAM, and partitioning memory into 'fast' and 'slow' regions to reduce latency, using a two-level virtual NUMA mechanism and extended page tables to identify and migrate hot pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PMEM is exposed as storage device rather than memory, then PMEM can be used in conventional systems, but PMEM cannot be used directly by applications and system efficiency is reduced
Solution Approach 1:
The patent introduces a caching component as an intermediary layer between PMEM and applications. This caching component transparently manages data transfer between PMEM and DRAM, allowing applications to directly access PMEM while maintaining high-speed access through the cache. The intermediary resolves the contradiction by enabling direct PMEM usage without requiring application changes or sacrificing performance.
Solution Approach 2:
The patent implements a caching mechanism that creates copies of frequently accessed data in DRAM from PMEM. This copying approach allows the system to maintain fast access speeds for hot data while preserving the high-density storage capacity of PMEM. The copy resides in DRAM for rapid access, eliminating the performance penalty of direct PMEM access.
2Quantity of substance
If PMEM is used directly without caching, then memory capacity is increased, but access speed decreases significantly (10x-50x slower than DRAM)
Solution Approach 1:
The patent applies local quality by differentiating between hot and cold data, and providing different access paths for each. Frequently accessed (hot) data is cached in fast DRAM, while less frequently accessed (cold) data remains in PMEM. This localized optimization ensures that the most performance-critical data accesses occur at high speed, while maintaining overall high memory capacity through PMEM.
Solution Approach 2:
The patent segments the memory system into two distinct layers: a fast DRAM cache layer for hot data and a high-capacity PMEM layer for cold data. This segmentation allows the system to optimize for both speed and capacity simultaneously by directing access patterns to appropriate memory layers based on data characteristics and access frequency.
3Ease of operation
If conventional NUMA mechanisms are used, then local memory access is optimized, but they are insufficient for PMEM speed differences (only address 1-1.5x latency difference, not 10x-50x)
Solution Approach 1:
The patent implements dynamic memory management where the caching component continuously monitors access patterns and adaptively transfers data between PMEM and DRAM based on real-time hot/cold data identification. This dynamic approach contrasts with static NUMA configurations, allowing the system to respond to changing workload requirements and maintain optimal performance across varying access patterns.
Solution Approach 2:
The patent fundamentally changes the memory hierarchy parameters by introducing a caching layer that actively manages data placement based on access frequency. This parameter change transforms the static memory architecture into a dynamic one where data location is determined by usage patterns rather than fixed physical positioning, enabling the system to handle the much larger latency gap between PMEM and DRAM.
Data Source
AI summary
Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be migrated to a target memory page in a second byte-addressable memory, the target memory page comprising one of a target host memory page and a target guest memory page, the second byte-addressable memory having an access speed faster than an access speed of the first byte-addressable memory.