Auto-Power On PMIC Mode for Biased Memory Testing
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Solution Overview
Problem
Existing memory testing systems fail to support biased testing of memory systems with integrated Power Management Integrated Circuits (PMICs) due to communication issues and significant messaging or processing overhead, as they require explicit commands to apply a bias, which can be unsupported in test environments.
Innovation Solution
Implementing an auto-power on mode for PMICs, allowing them to automatically apply a bias to memory devices upon receiving power, independent of explicit commands, thereby enabling biased testing without the need for command communication during the testing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If explicit commands are used to apply bias to memory devices through PMIC, then the testing can be controlled, but the messaging overhead and communication requirements increase significantly
Solution Approach 1:
The PMIC is programmed in advance to automatically apply bias to memory devices upon detecting power receipt, eliminating the need for real-time communication commands during testing. This preliminary configuration resolves the contradiction by pre-establishing the bias application behavior, thereby maintaining testing control while eliminating messaging overhead during the actual test execution
2Reliability
If explicit commands are sent to PMIC to apply bias, then the testing process can be monitored, but the test environment complexity increases due to communication requirements
Solution Approach 1:
The complex communication and command interface requirements are extracted and eliminated from the test environment. Instead of requiring sophisticated communication protocols between the test system and PMIC, the solution uses simple power presence detection that any test environment can provide, thereby maintaining testing capability while dramatically reducing test environment complexity
3Reliability
If the PMIC waits for commands to apply bias, then power management control is maintained, but testing latency increases
Solution Approach 1:
The PMIC is configured to autonomously detect power receipt and automatically apply bias to memory devices without waiting for external commands. This self-service mechanism resolves the contradiction by enabling the PMIC to independently perform the bias application function, thereby eliminating testing latency while maintaining power management control through pre-programmed logic
Data Source
AI summary
Methods, systems, and devices supporting an auto-power on mode for biased testing of a power management integrated circuit (PMIC) are described. A system may program a PMIC of a memory system to a specific mode. The mode may cause the PMIC to apply a bias to a memory device of the memory system upon receiving power and independent of a command to apply the bias to the memory device. The system may transmit power to the memory system while controlling one or more operating conditions (e.g., temperature, humidity) for a threshold time. The PMIC may apply a bias to the memory device during the threshold time based on the PMIC being programmed to the mode and the transmitted power. The system may identify a capability or defect of the memory device resulting from transmitting the power to the memory system while controlling the operating conditions for the threshold time.