PMIC Fault Reporting Structure for Capacitor Set Isolation
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Solution Overview
Problem
Existing power loss prevention circuits in power management integrated circuits (PMICs) face challenges in maintaining power to application devices during failures, as they lack effective mechanisms to isolate failed storage capacitors without impacting operational ones, leading to potential power loss and overcurrent protection issues.
Innovation Solution
An integrated circuit (IC) with a disconnect circuit and controller that connects and disconnects input voltage to output voltage based on power availability, using a bidirectional buck-boost converter to charge storage capacitors and provide bus voltage from operational sets during power loss, while isolating failed capacitors through separate blocking circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a blocking transistor is turned OFF to disconnect all storage capacitors when one fails, then overcurrent protection is achieved, but power loss protection capability is lost
Solution Approach 1:
The patent divides the storage capacitor system into multiple independent sets (first set and second set), each with its own blocking transistor (first and second blocking transistors). This segmentation allows selective disconnection of failed capacitors while maintaining connection to operational ones, resolving the contradiction between overcurrent protection and power loss protection capability.
Solution Approach 2:
The controller monitors the health status of storage capacitors and dynamically controls the blocking transistors based on detected failures. When a capacitor fails, the controller activates the corresponding blocking transistor to disconnect only the failed set, while keeping operational sets connected for power loss protection, achieving both overcurrent and power loss protection simultaneously.
2Object-affected harmful factors
If all storage capacitors are disconnected from a single PMIC when one fails, then system safety is maintained, but power backup capability is eliminated
Solution Approach 1:
The patent implements separate connection paths for multiple storage capacitor sets to the PMIC through individual blocking transistors. This allows the system to maintain safety by disconnecting only failed capacitor sets while keeping operational sets connected, thereby preserving power backup capability throughout the extended period.
Solution Approach 2:
The system dynamically changes the connection state parameters of blocking transistors based on capacitor health status. When capacitors fail, the corresponding blocking transistors switch from conductive to blocking state, isolating failed components while maintaining power backup function through operational capacitors, thus extending effective power backup duration.
3Reliability
If multiple sets of storage capacitors are used to extend power backup time, then power loss protection is improved, but complexity of capacitor management increases
Solution Approach 1:
The patent organizes multiple storage capacitor sets into independently manageable units, each with dedicated blocking transistors and control logic. This modular segmentation simplifies management by allowing the controller to handle each set independently based on its health status, reducing overall system complexity despite having multiple capacitor sets for extended power backup.
Solution Approach 2:
The controller is designed with universal functionality to manage multiple storage capacitor sets through a unified control mechanism. It can detect failures, activate blocking transistors, and maintain power loss protection across all sets using the same control logic, thereby improving power loss protection without proportionally increasing management complexity.
Data Source
AI summary
A power management integrated circuit (PMIC) chip for providing power loss protection to an application device. The PMIC chip may be adapted to co-work with a plurality sets of storage capacitors that are charged using power from a power source during normal operation. An application device receives power from the power source during normal operation and receives power from an operational set of storage capacitors during power loss. A failing set of storage capacitors is disconnected from an operational set of storage capacitors and from the PMIC chip. The operational set of storage capacitors remains connected to the PMIC chip to provide power loss protection.