Bidirectional PMIC Clock Interface for Fewer Master-Slave Terminals

Solution Overview

Problem

The existing semiconductor devices, particularly power management ICs (PMICs), face challenges in reducing the number of terminals to achieve a smaller package size, which is essential for compact designs such as in-vehicle systems.

Innovation Solution

The semiconductor device configuration integrates a clock terminal for both clock input and output, a data terminal for synchronized data transfer, and optional oscillators for system and DC/DC clock generation, allowing for shared clock usage between synchronization and data transfer, thereby eliminating the need for a dedicated synchronization clock terminal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dedicated synchronization clock terminal is added for clock input, then clock synchronization between master and slave devices is improved, but the number of terminals increases

Engineering Contradiction:

Improveclock synchronizationVSAvoidnumber of terminals

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The clock terminal is designed to serve multiple functions: it can output clocks from the master device and accept clocks from external sources for slave devices. This multi-functional design eliminates the need for separate dedicated clock input and output terminals, reducing the total terminal count while maintaining synchronization capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the clock input and clock output functions into a single bidirectional clock terminal. By merging these functions, the system reduces the number of terminals required while ensuring reliable clock synchronization between master and slave devices through the shared terminal.

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If separate clock terminals are used for clock input and output, then clock signal integrity is improved, but the package size increases

Engineering Contradiction:

Improveclock signal integrityVSAvoidpackage size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The clock terminal is designed to serve multiple functions: it can output clocks from the master device and accept clocks from external sources for slave devices. This multi-functional design eliminates the need for separate dedicated clock input and output terminals, reducing the total terminal count while maintaining synchronization capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the clock input and clock output functions into a single bidirectional clock terminal. By merging these functions, the system reduces the number of terminals required while ensuring reliable clock synchronization between master and slave devices through the shared terminal.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11853139B2Clock and data signal transmission in a master/slave PMIC system

Publication Date: 2023.12.26 ROHM CO LTD

AI summary

A semiconductor device includes a clock terminal to and from which a clock is allowed to be input and output, and a data terminal to and from which data is allowed to be input and output. In the semiconductor device, the data synchronized with the clock that is input to the clock terminal or is output from the clock terminal is output from the data terminal, and when the clock is output from the clock terminal, the clock is output irrespective of whether or not data transfer of the data is being executed.