Master-Slave PMIC Synchronization via Clock Pulse Counting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing power management systems, particularly those using multiple DC-DC converters, lack flexibility and synchronization in controlling different power rails, making them inadequate for diverse application requirements.
Innovation Solution
A power supply system comprising a master PMIC and slave PMICs, where all PMICs are coupled through enable and clock pins, allowing for synchronized power on and off sequences based on voltage thresholds and clock pulse counting, ensuring all PMICs are ready before initiating power operations and pausing sequences if any PMIC is not ready.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chained system connection control scheme is used to control multiple PMICs, then device complexity is reduced, but synchronization between different power rails cannot be achieved
Solution Approach 1:
The patent introduces a master PMIC as an intermediary that generates and distributes clock signals to all slave PMICs. This master PMIC acts as a central coordinator that enables synchronized power rail control across multiple PMICs without requiring complex interconnections between each PMIC pair. The clock pin serving as the communication channel between master and slave PMICs exemplifies this intermediary approach.
Solution Approach 2:
The patent segments the control system into a hierarchical structure with one master PMIC and multiple slave PMICs. This segmentation allows the synchronization function to be centralized in the master PMIC while keeping individual slave PMICs simpler. Each slave PMIC independently receives and responds to clock signals from the master, achieving system-wide synchronization through this segmented architecture.
2Adaptability or versatility
If conventional control scheme is used for power management, then ease of operation is maintained, but flexibility to cover different application requirements is insufficient
Solution Approach 1:
The patent implements dynamic control capabilities by allowing the master PMIC to generate clock signals with adjustable frequencies and duty cycles. The enable pin can dynamically control the power state (on/off) of slave PMICs based on system requirements. This dynamic behavior enables the system to adapt to different application scenarios while maintaining a unified control interface that preserves ease of operation.
Solution Approach 2:
The patent utilizes parameter changes in the clock signals (frequency, duty cycle, pulse width) to achieve different power management modes. By varying these clock parameters, the system can accommodate different application requirements such as different power-up sequences, power-down timing, and power rail synchronization intervals, all while using the same basic control mechanism.
Data Source
AI summary
A power supply having at least one PMIC provides flexible control to the power manage systems. The PMIC has an enable pin configured to receive a control signal, and a clock pin configured to generate and/or receive a series of clock pulses, so as to facilitate the operation of the PMIC.