PMIC Group Delay Detection for RF Power Amplifier Timing Alignment

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Solution Overview

Problem

In 5G-NR mobile communication devices, the modulated voltage and current in power amplifiers experience different group delays, leading to misalignment and degradation of error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) in RF signals due to propagation attenuation and interference in the mmWave RF spectrum.

Innovation Solution

A group delay determination circuit within the PMIC determines the relative group delay between the modulated voltage and current using known signals, allowing for time alignment and improving EVM and ACLR by generating rectangular signals with controlled rising and falling edges and adjusting delays to synchronize these signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If power amplifier circuit amplifies RF signal based on modulated voltage generated by PMIC, then data throughput is improved, but group delay misalignment between modulated voltage and modulated current degrades EVM and ACLR performance

Engineering Contradiction:
Improvedata throughputVSAvoidEVM and ACLR performance
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by determining the group delay difference between the modulated voltage and modulated current paths before RF signal transmission. The PMIC measures the group delay of the modulated current internally, calculates the difference from the known modulated voltage group delay, and uses this pre-determined value to compensate for misalignment, thereby preventing EVM and ACLR degradation before it occurs

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by having the PMIC continuously monitor and measure the group delay of the modulated current path, compare it with the known modulated voltage group delay, and use this feedback information to adjust timing alignment. This closed-loop feedback mechanism ensures that the power amplifier circuit maintains optimal EVM and ACLR performance while achieving high data throughput

Inventive Principle:
Principle #23Feedback

2Power

If modulated voltage and modulated current experience different group delays in power amplifier circuit, then signal amplification is achieved, but time misalignment occurs between voltage and current signals

Engineering Contradiction:
Improvesignal amplificationVSAvoidtime misalignment between voltage and current
Core Design Contradiction:
PowerVSLoss of time

Solution Approach 1:

The patent replaces physical/mechanical timing adjustment mechanisms with electronic/digital delay compensation. Instead of using mechanical variable delay lines or physical signal routing changes, the PMIC uses digital signal processing to calculate and apply the appropriate delay compensation based on the measured group delay difference, achieving precise time alignment without mechanical components

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent applies parameter changes by dynamically adjusting the delay parameter of the modulated voltage or modulated current based on the measured group delay difference. The PMIC modifies the timing parameter (delay value) to compensate for the inherent group delay mismatch between voltage and current paths, thereby achieving time alignment while maintaining signal amplification

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12388429B2Group delay determination in a communication circuit
Publication Date: 2025.08.12 QORVO US INC
  • US12388429B2 patent drawing
  • US12388429B2 patent drawing
  • US12388429B2 patent drawing

AI summary

Group delay determination in a communication circuit is disclosed. The communication circuit includes a power amplifier circuit that amplifies a radio frequency (RF) signal based on a modulated voltage and a power management integrated circuit (PMIC) that generates the modulated voltage. Herein, the PMIC includes a group delay determination circuit to determine a relative group delay between the modulated voltage and a modulated current, which is internal to the power amplifier circuit and unknown to the PMIC, solely based on signals known to the PMIC. The determined relative group delay can help to time align the modulated voltage with the modulated current at the power amplifier circuit to improve error vector magnitude (EVM) and/or adjacent channel leakage ratio (ACLR). Further, by determining the relative group delay based on known signals to the PMIC, it is possible to achieve good time alignment between the modulated voltage and the modulated current.