Configurable Delay PMIC for Stable Power State Transitions
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Solution Overview
Problem
Existing power management systems face challenges in ensuring stable power state transitions without causing system instability or corruption, particularly when the operating system is running critical processes during power state changes, leading to potential data loss or system malfunction.
Innovation Solution
A power management integrated circuit (PMIC) is designed to introduce a configurable delay between the receipt of a power state transition command and the start of the transition, allowing the operating system to safely terminate processes and store system state before power is removed, thus reducing the risk of corruption and eliminating the need for complex handshaking arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power state transition is initiated immediately, then power consumption is reduced and battery life is improved, but system stability deteriorates and data corruption may occur
Solution Approach 1:
The patent applies preliminary action by introducing a delay mechanism that allows the operating system to complete critical processes and store system state before power is actually removed. The PMIC receives the power state transition command but waits for a predetermined period during which the OS can perform necessary shutdown actions, ensuring system stability while still achieving power savings.
2Reliability
If complex handshaking arrangements are implemented to ensure stable power transitions, then system reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the complex handshaking logic from the hardware domain and relocates it to the software domain. Instead of implementing complex hardware handshaking mechanisms between the PMIC and operating system, the solution uses a simple delay mechanism combined with OS-level process management to achieve the same reliability goal with significantly reduced hardware complexity.
3Reliability
If power state transition delay is increased to allow process termination, then system stability is improved, but transition speed decreases
Solution Approach 1:
The patent applies parameter changes by making the delay duration configurable rather than fixed. The delay parameter can be adjusted based on the specific requirements of different operating systems and device configurations, allowing optimization between system stability and transition speed. This configurable parameter approach enables the system to adapt the delay length to match the actual process termination requirements.
Data Source
AI summary
Power management integrated circuits (PMICs) and related methods. In one aspect a PMIC which is operable to provide a plurality of PMIC power states is arranged to provide a predetermined delay before a power state transition. The delay is applied after receipt by the PMIC control circuitry of a power state transition command. Applying a delay allows time for the system powered by the PMIC to perform any necessary shut-down procedures and terminate active processes before power is removed, preventing corruption of the system. The delay is preferably configurable. The PMIC may also be arranged to control power converters which are external to the PMIC. In another aspect the PMIC has translation circuitry for providing the control settings of one power block, e.g. power converter, with any necessary modifications to be used by another power block. This means that only one set of control settings needs to be updated to change the output of both power blocks simultaneously.