PMIC Diagnostic Registers for Power-Up Fault Analysis
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Solution Overview
Problem
Power management integrated circuits (PMICs) face challenges in diagnosing internal fault conditions due to limited visibility into internal state during power up issues, making it difficult to reproduce and address rare and intermittent problems.
Innovation Solution
Incorporating diagnostic registers that store and maintain signal states of digital command and clock signals, allowing retrieval even when the PMIC is powered down, along with a reset signal generator to facilitate recovery and analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If diagnostic registers are added to store signal states, then diagnostic capability is improved, but device complexity increases
Solution Approach 1:
The diagnostic registers are integrated into the existing power management integrated circuit to serve multiple functions: storing signal states during power up issues, maintaining states after power down, and enabling root cause analysis. This multi-functional approach improves diagnostic capability without requiring entirely separate diagnostic hardware, thereby limiting the increase in device complexity.
Solution Approach 2:
The diagnostic registers capture and store signal states at the moment of fault occurrence (during power up issues) before the system fully powers down. This preliminary action preserves critical diagnostic information that would otherwise be lost, enabling later analysis without requiring the system to remain in the fault state.
2Measurement precision
If signal states are maintained after power down, then root cause analysis capability is improved, but energy consumption increases
Solution Approach 1:
Instead of maintaining the entire system state after power down, only the critical signal states relevant to diagnostic analysis are preserved in the diagnostic registers. This localized approach maintains necessary diagnostic information while minimizing energy consumption by keeping only essential data in a low-power state.
Solution Approach 2:
The diagnostic registers use a simple, low-cost storage mechanism that maintains signal states temporarily after power down without requiring continuous power supply. This disposable-like approach preserves diagnostic information sufficiently for analysis while avoiding the energy cost of maintaining full system operation.
3Ease of operation
If diagnostic registers are accessible while powered down, then troubleshooting effectiveness is improved, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary interface that allows access to diagnostic register data while the system is powered down. This intermediary layer enables troubleshooting personnel to retrieve stored signal states without requiring the main system to be operational, improving troubleshooting effectiveness while isolating the complexity to a specific access mechanism rather than the entire system.
Data Source
AI summary
In one embodiment, a power management integrated circuit comprises a finite state machine having a first terminal to receive a digital command signal, a second terminal to receive a clock signal, and a third terminal to receive a first reset signal to reset the finite state machine into a predetermined operational state. A plurality of diagnostic registers is configured to store a signal state of the digital command signal or a clock state of the clock signal, or both in response to the first reset signal. The diagnostic registers are configured to maintain the signal state or the clock state, or both after powering down of the power management integrated circuit in response to the first reset signal. The diagnostic registers are configured to allow retrieval of the stored signal state or the stored clock state, or both upon power on of the power management integrated circuit.