Delay-Compensating PMIC for RF Envelope Alignment
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Solution Overview
Problem
Existing power management integrated circuits (PMICs) for 5G-NR mobile communication devices suffer from inherent processing delays that cause misalignment between the time-variant voltage and the time-variant power envelope of RF signals, leading to amplitude distortion and reduced data throughput due to propagation attenuation and interference in the mmWave RF spectrum.
Innovation Solution
A delay-compensating PMIC is designed with a target voltage circuit that includes an envelope detector, an analog lookup table (LUT) circuit, and a voltage processing circuit to generate a modified target voltage that is time-adjusted to offset processing delays, ensuring better alignment with the time-variant envelope of the analog signal and reducing amplitude distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a power management circuit is used to generate time-variant voltage for power amplifier, then operating efficiency of power amplifier is improved, but processing delay causes misalignment between voltage and power envelope leading to amplitude distortion
Solution Approach 1:
The patent applies preliminary action by predicting future values of the power envelope based on historical data and trend analysis. The system calculates predicted values ahead of time to compensate for processing delays, ensuring that the voltage signal aligns with the actual power envelope when delivered to the power amplifier. This predictive approach allows the system to maintain precision despite inherent processing delays in the power management circuit.
2Manufacturing precision
If processing delay is reduced in target voltage circuit, then alignment between time-variant voltage and power envelope is improved, but circuit complexity and processing requirements increase
Solution Approach 1:
The patent uses copying by creating a predicted model of the power envelope based on historical data patterns. Instead of directly processing the real-time complex signals with high complexity circuits, the system generates a copied representation (predicted values) that mirrors the essential characteristics of the power envelope. This copied predictive model simplifies the processing requirements while maintaining alignment precision.
3Loss of energy
If envelope tracking is implemented to improve power amplifier efficiency, then energy loss is reduced, but processing delay causes signal clipping and distortion
Solution Approach 1:
The patent implements feedback by continuously monitoring the actual power envelope and comparing it with predicted values. The system uses this feedback to adjust and refine its predictions, ensuring that the voltage signal remains accurately aligned with the power envelope. This closed-loop feedback mechanism maintains signal quality and prevents clipping while preserving the energy efficiency benefits of envelope tracking.
Data Source
AI summary
A delay-compensating power management integrated circuit (PMIC) is provided. The PMIC includes a target voltage circuit configured to generate a target voltage that is utilized for generating a time-variant voltage to amplify an analog signal. The target voltage is generated based on a time-variant envelope of the analog signal but lags behind the time-variant envelope by a temporal delay(s) due to an inherent processing delay in the target voltage circuit. In this regard, a voltage processing circuit is provided in the target voltage circuit to generate a modified target voltage that is time-adjusted relative to the target voltage to substantially offset the temporal delay(s). By generating the time-variant voltage based on the modified target voltage, the time-variant voltage can be better aligned with the time-variant envelope of the analog signal, thus helping to reduce amplitude distortion when amplifying the analog signal.