Master-Slave PMIC Handshaking for Safe Power Mode Transitions
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Solution Overview
Problem
Existing power management systems in safety-critical applications, such as automotive and industrial systems, face challenges in ensuring robust and safe transitions between normal and low power modes due to potential miscommunication between master and slave PMICs, which can lead to unexpected power downs and safety risks.
Innovation Solution
A power supply system comprising master and slave power management circuitry, where the master PMIC provides supply voltage and core voltage, and includes comparator circuitry to monitor voltage levels and control circuitry to manage transitions between normal and low power modes by asserting and de-asserting signals to ensure safe and robust power mode changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a master PMIC and slave PMIC configuration is used to provide multiple supply voltages, then the power supply capability and versatility are improved, but the risk of miscommunication between PMICs increases, leading to potential unexpected power downs and safety issues
Solution Approach 1:
The patent implements a feedback mechanism where the master PMIC monitors the slave PMIC's power good signal to determine when the slave PMIC has successfully transitioned to a new power mode before the master PMIC changes its output. This feedback loop ensures coordinated operation between master and slave PMICs, preventing miscommunication and unexpected power downs while maintaining the ability to provide multiple supply voltages.
Solution Approach 2:
The patent employs preliminary action by having the master PMIC wait for confirmation from the slave PMIC (via the power good signal) before completing its own power mode transition. This ensures that the slave PMIC is ready to handle the load before the master PMIC changes its output, preventing power disruption while maintaining system versatility.
2Use of energy by moving object
If power mode transitions are implemented to minimize power consumption during low activity, then energy efficiency is improved, but the risk of incorrect power removal and unexpected system shutdown increases
Solution Approach 1:
The patent uses feedback signals (power good signals) from both master and slave PMICs to confirm successful power mode transitions before allowing the system to enter low power mode. This ensures that power is not removed at an incorrect time, preventing unexpected shutdowns while achieving energy efficiency through proper low power mode operation.
Solution Approach 2:
The patent implements preliminary verification through power good signals that confirm the slave PMIC has successfully taken over power delivery before the master PMIC transitions to low power mode. This preliminary action ensures safe power mode transitions by verifying system readiness before reducing power consumption.
3Reliability
If monitoring of voltage levels is implemented to ensure safe transitions, then the reliability of power mode transitions is improved, but the device complexity increases due to additional comparator circuitry and control logic
Solution Approach 1:
The patent employs self-service by utilizing the slave PMIC's inherent power good signal output to provide feedback to the master PMIC. This eliminates the need for additional complex monitoring circuitry, as the slave PMIC automatically generates the confirmation signal that indicates successful power mode transition, maintaining reliability without significantly increasing device complexity.
Data Source
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AI summary
A cascaded power system including master power management circuitry and slave power management circuitry. The master circuitry includes a master power regulator, comparator circuitry, and control circuitry. The power regulator provides a supply voltage during a normal mode and discharges the supply voltage during a low power mode. The slave circuitry provides a core voltage when enabled and otherwise discharges the core voltage. The comparator circuitry monitors the voltage levels of the supply and core voltages and the control circuitry performs handshaking with the slave circuitry based partly on the voltages to ensure smooth transitioning between the normal and low power modes. The control circuitry asserts a low power good signal when the supply and core voltages are discharged, and de-asserts the low power good signal when the supply and core voltages are fully charged. A processor may rely on the low power mode signal for transitioning between power modes.