PMIC Interface for Distributed Memory Power State Management
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Solution Overview
Problem
In distributed memory power management systems, the interfacing between the host and PMICs for changing power states is inefficient, leading to high time consumption and increased I/Os due to serial command issuance or excessive I/O activity on multiple I2C buses, which can result in power state transition latency and increased power consumption.
Innovation Solution
A novel PMIC/PMIC interface is introduced, where a master PMIC receives power state change commands from the host and forwards them to slave PMICs using a minimal I/O count two-pin interface, enabling multi-level signaling for efficient power state management, allowing PMICs to forward commands internally and reduce I/O complexity, thereby minimizing latency and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If serial command issuance is used to change power states of multiple PMICs, then I/O complexity is reduced, but time consumption and latency increase
Solution Approach 1:
The system segments PMICs into a hierarchical structure with one master PMIC and multiple slave PMICs. The master PMIC receives commands from the host and segments the command distribution task by forwarding to multiple slave PMICs simultaneously through parallel I2C buses, resolving the contradiction between reduced I/O complexity and minimized latency.
Solution Approach 2:
The master PMIC acts as an intermediary between the host and slave PMICs. It receives power state change commands from the host and mediates the distribution to multiple slave PMICs through parallel I2C buses, enabling efficient command propagation while maintaining manageable I/O complexity at the host interface.
2Loss of time
If multiple I2C buses are used to interface with multiple PMICs, then power state transition latency is reduced, but I/O activity and power consumption increase
Solution Approach 1:
The system uses multiple parallel I2C buses segmented to connect the master PMIC to multiple slave PMICs simultaneously. This segmentation enables concurrent command transmission to multiple PMICs, reducing power state transition latency while the master PMIC coordinates to minimize overall I/O activity and power consumption.
Solution Approach 2:
The system employs multiple I2C buses in parallel rather than a single bus, providing excessive I/O capacity that enables simultaneous command transmission to multiple PMICs. This partial redundancy of communication paths reduces latency while the coordinated control by the master PMIC ensures power consumption remains manageable.
3Productivity
If distributed PMIC architecture is used, then power management efficiency is improved, but I/O complexity and current draw increase
Solution Approach 1:
The distributed PMIC architecture segments power management functions across multiple PMICs, with one master PMIC coordinating and multiple slave PMICs executing power state changes. This segmentation improves power management efficiency by enabling parallel control while the hierarchical structure maintains manageable I/O complexity.
Solution Approach 2:
The master PMIC serves as an intermediary that receives commands from the host and distributes them to multiple slave PMICs through parallel I2C buses. This intermediary role enables efficient distributed power management while consolidating I/O complexity at the master PMIC interface, preventing excessive current draw on the host.
Data Source
Figure 1a~1b
Figure 2a
Figure 2b
AI summary
An apparatus is described. The apparatus includes a power management integrated circuit (PMIC) semiconductor chip having logic circuitry to implement a PMIC/PMIC interface having a downstream signal line and an upstream signal line. The downstream signal line to communicate any of multiple states that a downstream PMIC semiconductor chip is to implement with one of multiple voltage levels, where, different ones of the multiple voltage levels correspond to different ones of the multiple states. The upstream signal line is to communicate whether or not the downstream PMIC semiconductor chip is ready to receive a next one of the multiple voltage levels.