Stacked Semiconductor Package With PMIC Interposer for High Pin Density
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Solution Overview
Problem
There is a need for semiconductor packages that can accommodate multiple pins in a compact size while efficiently managing power and signal distribution between different semiconductor chips, which existing technologies have not adequately addressed.
Innovation Solution
A semiconductor package design featuring a first interposer package with a power management integrated circuit (PMIC), core member, redistribution layers, and core vias that electrically connect a first package with a second package, enabling power and signal path distribution between the two packages, and allowing for a multi-function double side interposer structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a compact package size is used, then the package dimensions are reduced, but the number of pins and power distribution capability are limited
Solution Approach 1:
The patent transitions from a planar pin arrangement to a three-dimensional vertical stacking architecture. Multiple semiconductor chips are stacked vertically with interposer packages in between, allowing multiple pins and power distribution networks to be accommodated in the vertical dimension rather than requiring expanded horizontal space. This enables compact footprint while maintaining high pin count capability.
Solution Approach 2:
The patent implements a nested structure where semiconductor chips are embedded within interposer packages, which themselves are integrated into the overall stacked package. The interposer packages contain redistribution layers and power management circuits that are nested within the vertical stack, allowing multiple functional elements to be contained within a compact volume.
2Adaptability or versatility
If multiple semiconductor chips are integrated in a stacked configuration, then the integration density is improved, but the power distribution and signal routing complexity increases
Solution Approach 1:
The patent introduces interposer packages as intermediary structures between stacked semiconductor chips. These interposers contain redistribution layers and power management integrated circuits that mediate the complex power distribution and signal routing requirements. The interposers act as buffer layers that simplify the connection interface between chips while handling the complexity of multi-voltage domain power distribution internally.
Solution Approach 2:
The interposer packages perform multiple functions simultaneously: they provide mechanical support for stacking, enable electrical redistribution through conductive layers, facilitate power management through integrated circuits, and enable thermal management pathways. This multi-functionality reduces the need for separate dedicated structures for each function, simplifying the overall power distribution architecture.
3Power
If power management integrated circuits are added to manage multiple chips, then the power distribution capability is improved, but the package thickness increases
Solution Approach 1:
The patent merges the power management integrated circuits directly into the interposer package structure rather than using separate external power management components. The PMICs are integrated within the same vertical stack as the semiconductor chips, with power distribution networks that traverse through the interposer substrate. This consolidation eliminates the need for additional external power management layers, maintaining compact thickness while providing comprehensive power management capability.
Data Source
AI summary
A semiconductor package includes: a first package including a first semiconductor chip; a second package under the first package, the second package including a second semiconductor chip; and a first interposer package between the first package and the second package, the first interposer package including: a power management integrated circuit (PMIC) configured to supply power to the first package and the second package; a core member having a through-hole in which the PMIC is disposed; a first redistribution layer on the core member, and electrically connected to the first package; a second redistribution layer under the core member, and electrically connected to the second package; core vias penetrating the core member, and electrically connecting the first redistribution layer with the second redistribution layer; and a first signal path electrically connecting the first package with the second package.