Power Management IC Latency-Aware Current Limit Messaging
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Solution Overview
Problem
In mobile communication devices, high bus latency in serial communication links affects power management and radio frequency operations, leading to sub-optimal performance and limited functionality due to indeterminate latency times and increased congestion.
Innovation Solution
Incorporating latency information in messages transmitted over a serial bus, specifically through a power management integrated circuit that generates and transmits a timestamp with extended current level messages, allowing devices to initiate mitigation closer to the end of a defined current limit time, thereby reducing uncertainties in arbitration and interface latencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple devices are concurrently active on a multi-drop serial bus, then device functionality and communication capability are improved, but bus latency increases and becomes indeterminate
Solution Approach 1:
The patent applies preliminary action by including a timestamp in the extended current level message that indicates the elapsed time between message generation and transmission start. This allows the receiving device to proactively compensate for bus latency by initiating current reduction at the correct time, rather than waiting for latency to manifest. The timestamp enables advance planning of power management actions despite uncertain bus access delays.
2Adaptability or versatility
If arbitration schemes are used to manage bus access, then device coexistence is improved, but latency becomes uncertain and performance limits are not met
Solution Approach 1:
The patent applies feedback by incorporating a timestamp in the extended current level message that provides information about the actual bus latency experienced. The receiving device uses this feedback to adjust its current reduction timing accordingly. This closed-loop approach allows the system to adapt to varying arbitration delays and maintain precise timing for power management actions despite uncertain bus access.
3Ease of operation
If extended current level messages are transmitted without latency information, then power management control is simplified, but timing precision for current reduction is degraded
Solution Approach 1:
The patent applies the intermediary principle by introducing a timestamp field as a mediator between the power management controller and the receiving device. This timestamp carries latency information that enables precise timing without complicating the overall control mechanism. The receiving device uses this intermediary data to calculate the exact time to initiate current reduction, maintaining timing precision while keeping the control protocol relatively simple.
Data Source
AI summary
Systems, methods, and apparatus for power management are disclosed. A power management integrated circuit has a bus interface circuit configured to couple the power management integrated circuit to a shared communication bus, one or more regulator circuits configured to provide current to a managed device, and a controller. The controller is configured to determine that current consumption by the managed device exceeds a threshold level, generate an extended current level message to be transmitted over the shared communication bus to the managed device and transmit a time value with the extended current level message, the time value indicative of an elapsed time between generation of the extended current level message and start of transmission of the extended current level message.