Memory PMIC Loopback Wake-Up During Low-Power States
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Solution Overview
Problem
Memory systems face challenges in efficiently managing power consumption during deactivated states, as components may not receive signals due to being powered down, leading to disrupted communication and inefficient power management.
Innovation Solution
The use of loopback signals through conductive paths between memory devices and a PMIC allows for reactivation of components, enabling the PMIC to transition from a deactivated state to an activated state by sending activation signals using loopback pins, thereby restoring communication and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the PMIC enters a deactivated state to conserve power, then energy consumption is reduced, but the PMIC cannot receive signals from memory devices
Solution Approach 1:
The patent segments the PMIC's operational states into deactivated and activated modes, allowing selective power management. During deactivated state, only essential circuits remain powered while other components are powered down, enabling the PMIC to maintain basic signal reception capability without full power consumption.
Solution Approach 2:
The patent introduces an intermediary wake-up signal mechanism that allows memory devices to communicate with the deactivated PMIC. This intermediary signal path enables the PMIC to receive activation commands even in low-power state, bridging the gap between power savings and communication reliability.
2Loss of energy
If components are powered down during sleep states, then energy conservation is improved, but communication between memory devices and PMIC is disrupted
Solution Approach 1:
The patent implements preliminary action by preparing wake-up signal pathways before the PMIC fully deactivates. The memory devices are configured to monitor and send wake-up signals through dedicated pins even as the PMIC transitions to sleep mode, ensuring communication continuity without full power consumption.
Solution Approach 2:
The patent applies local quality by maintaining power supply to specific communication circuits and pins while powering down other PMIC components. This selective power distribution allows the PMIC to receive and process wake-up signals locally without requiring full system activation, preserving communication capability while conserving energy.
Data Source
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AI summary
Techniques and devices for managing power consumption of a memory system using loopback are described. When a memory system is in a first state (e.g., a deactivated state), a host device may send a signal to change one or more components of the memory system to a second state (e.g., an activated state). The signal may be received by one or more memory devices, which may activate one or more components based on the signal. The one or more memory devices may send a second signal to a power management component, such as a power management integrated circuit (PMIC), using one or more techniques. The second signal may be received by the PMIC using a conductive path running between the memory devices and the PMIC. Based on receiving the second signal or some third signal that is based on the second signal, the PMIC may enter an activated state.