PMIC Master/Slave Mode Switching for SATA and PCIe Bus Adaptability

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Solution Overview

Problem

Conventional power management subsystems in storage systems are designed for specific bus types, requiring separate board designs and static master or slave functionalities, which limits their adaptability and efficiency across different bus types like PCIe and SATA.

Innovation Solution

A Power Management Integrated Circuit (PMIC) that can operate in both master and slave modes on various buses, enabling real-time switching of power management roles and consolidating power management functionality into a single board design, allowing for efficient power management across different bus types.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional power management subsystems are designed for specific bus types with dedicated master or slave functionalities, then they can reliably manage power for that specific bus type, but they require separate board designs and cannot adapt to different bus types like PCIe and SATA

Engineering Contradiction:
Improveadaptability across different bus typesVSAvoidseparate board designs for different bus types
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The PMIC is designed to perform multiple functions by operating in both master and slave modes, allowing a single board design to support different bus types (PCIe and SATA). The PMIC can dynamically switch between being a power management master for SATA buses and a power management slave for PCIe buses, eliminating the need for separate board designs for different bus types.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The PMIC dynamically changes its operational mode based on the bus type it is connected to. It can switch between master and slave functionalities in real-time, adapting its power management role according to the specific bus configuration. This dynamic capability allows the same hardware to serve multiple purposes without requiring physical redesign.

Inventive Principle:
Principle #15Dynamics

2Ease of operation

If the PMIC operates in master mode for SATA buses, then it can independently manage power mode transitions, but it must switch to slave mode for PCIe buses where the controller acts as master

Engineering Contradiction:
Improveindependent power management controlVSAvoidcompatibility with different bus control architectures
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The PMIC dynamically adjusts its operational role based on the bus type. For SATA buses, it operates in master mode to independently manage power transitions. For PCIe buses, it switches to slave mode to work under controller management. This dynamic role switching enables the PMIC to maintain ease of operation while adapting to different bus control architectures.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The PMIC changes its operational parameters (master/slave mode) according to the specific bus type it is connected to. This parameter change allows it to maintain optimal control characteristics for each bus type while preserving compatibility with different control architectures through a unified hardware design.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If separate board designs are used for different bus types, then each board can be optimized for its specific bus type, but it increases manufacturing complexity and reduces adaptability in data centers

Engineering Contradiction:
Improvebus-type-specific optimizationVSAvoidmanufacturing complexity with separate board designs
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The PMIC provides bus-type-specific optimization through its multi-functional capability. A single universal PMIC design can operate optimally with both SATA and PCIe buses by dynamically switching between master and slave modes. This eliminates the need for separate optimized board designs for different bus types, thereby reducing manufacturing complexity while maintaining reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Adaptability or versatility

If the PMIC supports real-time switching between master and slave modes, then it enhances adaptability and saves board area, but it requires complex mode switching logic and control mechanisms

Engineering Contradiction:
Improvereal-time mode switching capabilityVSAvoidmode switching control mechanisms
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The PMIC incorporates dynamic mode switching capability that automatically adapts to the connected bus type. The mode switching logic is integrated into the PMIC's operational framework, allowing it to transition between master and slave modes based on detected bus characteristics. This dynamic approach enhances adaptability while managing the complexity of mode switching through automated detection and transition protocols.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11614872B2Power management integrated circuit (PMIC) master/slave functionality
Publication Date: 2023.03.28 MICRON TECHNOLOGY INC
  • US11614872B2 patent drawing
  • US11614872B2 patent drawing
  • US11614872B2 patent drawing

AI summary

A power management integrated circuit (PMIC) capable of operating, in memory systems, as a master control in power management in some situations and operating as a slave control in power management in other situations. For example, when used in a memory system operating on a SATA bus, the PMIC assumes the master control by monitoring the bus signals for entering or existing a sleep mode or a power shutdown mode, communicating to the controller of the memory system to prepare for the respective mode, and when ready, adjusting power states for the mode changes. For example, when used in a memory system operating on a PCIe bus, the PMIC assumes the slave control during a normal mode and a sleep mode, but the master control when the memory system is in a power disable mode in which the controller of the memory system is powered off.