Memory PMIC Rail Threshold Feedback for Safe Power Cycling
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Solution Overview
Problem
Conventional memory sub-systems face challenges in ensuring that voltage rails reach sufficient threshold levels before power cycling events, leading to potential damage and leakage issues due to insufficient bleed resistor methods and costly dedicated pins.
Innovation Solution
Active monitoring of power management component output voltages using a control component to ensure all voltage rails meet respective threshold levels before allowing memory sub-system events, such as reboot, through feedback circuitry and comparators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bleed resistor methods are used to ensure voltage rails reach threshold levels, then power cycling safety is improved, but device complexity and cost increase due to insufficient effectiveness and requirement for dedicated pins
Solution Approach 1:
The patent implements active monitoring of voltage rail levels through feedback circuitry that continuously checks whether voltage rails have reached their threshold levels before allowing power cycling events. The control component receives feedback signals from comparators that compare actual voltage rail levels against predetermined thresholds, and uses this feedback to determine when it is safe to proceed with power cycling, thereby ensuring reliability without requiring complex dedicated pins or bleed resistors for each voltage rail
Solution Approach 2:
The power management component performs self-monitoring of its own output voltage levels using integrated comparators and feedback circuitry. The control component autonomously determines when voltage rails have reached sufficient threshold levels and decides when power cycling can safely occur, eliminating the need for external monitoring circuits or dedicated pins for each voltage rail, thus reducing device complexity while maintaining safety
2Measurement precision
If dedicated pins are used to monitor voltage rail levels, then measurement precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent employs a universal monitoring approach where a single control component with integrated comparators monitors multiple voltage rails sharing common feedback circuitry. Instead of requiring dedicated pins for each voltage rail, the system uses a multi-functional monitoring mechanism that can check any number of voltage rails through the shared comparator infrastructure, thereby achieving precise measurement without proportionally increasing manufacturing cost
Solution Approach 2:
The patent merges the monitoring functions for multiple voltage rails into a single integrated control component. The comparators and feedback circuitry are combined within the power management component, allowing simultaneous monitoring of multiple voltage levels without requiring separate dedicated pins for each rail. This consolidation achieves precise voltage level measurement while reducing the overall pin count and manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures safe and efficient power cycling by preventing adverse effects on memory sub-system components and reducing the need for costly dedicated pins and bleed resistors.
Implementation Method 1
the comparator can be configured to compare the output voltage of the regulator to a reference voltage and to generate a feedback signal in response to the comparison
Data Source
AI summary
A memory sub-system comprises a power management component comprising a plurality of regulators configured to output respective operating voltages for the memory sub-system. The power management component comprises a power management integrated circuit (PMIC) and is configured to monitor voltage levels of the plurality of regulators and prevent an event of the memory sub-system from occurring until the monitored voltage levels of a set of the plurality of regulators are determined to have reached respective threshold voltage levels.


