Delay-Compensating PMIC Circuit for RF Envelope Alignment
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Solution Overview
Problem
Existing power management circuits in mobile communication devices often experience misalignment between the time-variant target voltage and the time-variant power envelope of RF signals, leading to amplitude clipping and distortion during signal amplification.
Innovation Solution
A delay-compensating power management circuit that includes a PMIC and a voltage processing circuit. The voltage processing circuit determines the temporal offset between the time-variant power envelope and the time-variant target voltage, modifying the target voltage to realign it with the power envelope, thereby reducing distortions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the transceiver circuit sends the time-variant target voltage to the power management circuit via a communication bus, then the power management circuit can generate the supply voltage based on the target voltage, but the time-variant target voltage becomes misaligned from the time-variant power envelope when arrived at the power management circuit
Solution Approach 1:
The voltage processing circuit performs preliminary action by determining the temporal offset between the time-variant power envelope and the time-variant target voltage, and modifying the target voltage in advance to compensate for the delay before the supply voltage is generated. This ensures that the supply voltage remains aligned with the power envelope despite transmission delays through the communication bus.
2Ease of operation
If the supply voltage is misaligned with the time-variant power envelope, then the power management circuit can operate independently, but amplitude clipping and distortion occur during signal amplification
Solution Approach 1:
The voltage processing circuit implements feedback by continuously monitoring the temporal relationship between the time-variant power envelope and the time-variant target voltage, determining the temporal offset, and adjusting the target voltage accordingly. This feedback mechanism ensures that the supply voltage remains properly aligned with the power envelope, preventing amplitude clipping and distortion while allowing the power management circuit to operate independently.
Data Source
AI summary
A delay-compensating power management circuit is provided. The power management circuit includes a power management integrated circuit (PMIC) configured to generate a time-variant voltage(s) based on a time-variant target voltage(s) for amplifying an analog signal(s) associated with a time-variant power envelope(s). A voltage processing circuit is provided in the power management circuit to determine a temporal offset, which can be positive or negative, between the time-variant power envelope(s) and the time-variant target voltage(s). Accordingly, the voltage processing circuit modifies the time-variant target voltage(s) to substantially reduce the determined temporal offset and thereby realign the time-variant target voltage(s) with the time-variant power envelope(s). By realigning the time variant target voltage(s) with the time-variant power envelope(s), it is possible to align the time-variant voltage(s) with the time-variant power envelope(s) to reduce distortions (e.g., amplitude clipping) during amplification of the analog signal.