Main-Sub PMIC Sequencing for Low-Standby Power Management
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Solution Overview
Problem
The increased physical footprint and thermal load of large PMICs in SoCs lead to high operation costs and complexity, necessitating multiple PMICs that disperse thermal loads and complicate external component placement, while existing power management systems consume excessive current during standby periods.
Innovation Solution
A power management device comprising a main PMIC and sub PMICs that communicate through dedicated pins, enabling initial operations during standby using a sub enable signal to activate functions concurrently or sequentially, reducing standby current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If multiple PMICs are used to disperse thermal load and reduce physical footprint, then thermal management and layout complexity are improved, but device complexity and communication overhead increase
Solution Approach 1:
The power management function is divided into a main PMIC and multiple sub PMICs, each handling specific power domains. This segmentation disperses thermal load across multiple smaller ICs and simplifies the power management architecture by delegating specific functions to sub PMICs while the main PMIC handles coordination.
Solution Approach 2:
The main PMIC acts as an intermediary that coordinates between the processor and sub PMICs. It generates control signals (such as sub enable signals) that manage the activation and operation of sub PMICs, simplifying the overall system control architecture while enabling distributed power management.
2Speed
If all PMIC functions are activated during standby period to ensure readiness, then system responsiveness is improved, but current consumption increases
Solution Approach 1:
The system dynamically activates only the necessary PMIC functions during standby periods. The main PMIC determines which sub PMICs need to be active based on system state, and selectively enables them through control signals. This dynamic activation approach maintains system responsiveness while minimizing standby current consumption by keeping unnecessary power management functions in low-power states.
Solution Approach 2:
During standby periods, only partial PMIC functions are activated - specifically only those sub PMICs that are necessary for maintaining basic system operation. The main PMIC selectively enables required sub PMICs while leaving others inactive, avoiding excessive activation of all possible functions and thereby reducing standby current consumption while maintaining adequate system responsiveness.
Data Source
AI summary
A power management device includes a main power management integrated circuit (PMIC) and at least one sub PMIC that communicates with the main PMIC through a dedicated pin. The main PMIC includes a first pin, enables first functions associated with a first initial operation based on a battery voltage during a stand-by period before generating first output voltages based on the battery voltage and applies a first sub enable signal to the at least one sub PMIC through the first pin based on a power-on signal after completing the first initial operation. The at least one sub PMIC includes a second pin, receives the first sub enable signal through the second pin and enables second functions associated with a second initial operation based on the battery voltage, in response to an activation of the first sub enable signal.