PMIC SMB Isolation for Memory Controller Power States
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Solution Overview
Problem
Existing memory sub-systems, such as SSDs, face challenges in managing system management bus (SMB) isolation during power transitions, leading to complications in accessing vital product data (VPD) and address resolution protocol (ARP) communications, particularly when the memory controller is powered down in low power states.
Innovation Solution
Integration of power management circuitry within a PMIC that buffers SMB signals to both a microcontroller and a memory controller, enabling automatic isolation and connection based on power states, thus ensuring seamless VPD and ARP communications regardless of power mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the memory controller is powered down in low power states, then power usage is reduced, but VPD and ARP communications cannot be accessed
Solution Approach 1:
The SMB interface functionality is segmented between two controllers: the memory controller handles SMB communications during normal power states, while the microcontroller takes over SMB communications during low power states. This segmentation allows the system to maintain VPD and ARP communication accessibility regardless of which controller is active, resolving the contradiction between power savings and communication reliability.
2Reliability
If separate SMB isolation devices are used to disconnect the SMB from the memory controller in low power mode, then communication reliability is maintained, but device complexity increases
Solution Approach 1:
The patent merges the SMB isolation function with the PMIC by integrating the hot swap SMB controller directly into the power management circuitry. This consolidation eliminates the need for separate external isolation devices, reducing component count and system complexity while maintaining reliable SMB communication during power transitions between normal and low power states.
3Volume of moving object
If power management circuitry and SMB routing are integrated into a single PMIC, then component size is reduced, but manufacturing complexity increases
Solution Approach 1:
The PMIC is designed with multi-functionality, incorporating both power management capabilities and SMB routing functions within a single integrated circuit. The hot swap SMB controller embedded in the PMIC can dynamically route SMB communications to either the memory controller or microcontroller based on power state, providing universal functionality that reduces overall system size while managing manufacturing complexity through standardized integration processes.
Data Source
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AI summary
A power management integrated circuit (PMIC) is described for providing system management bus (SMB) isolation, along with memory sub-systems which include such a PMIC and methods of operating such devices. In one embodiment, a PMIC comprises a voltage supply input, power management circuitry, and elements of a SMB. The SMB elements can include an SMB input, an SMB hot swap controller coupled to the SMB input, one or more SMBs, and one or more SMB outputs. When integrated with a memory sub-system, one SMB output can be connected to a memory controller and another SMB output to a microcontroller. During different power states (e.g., normal or low power states), certain outputs can be isolated in order to manage communications on the SMB during the different power states of the memory sub-system using the PMIC.