PMIC Supply Clock Phasing for Multi-Converter EMI Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power management integrated circuits (PMICs) face issues with electromagnetic interference (EMI) due to constant frequency operating switching converters, leading to errors and increased capacitance in input filter capacitors, which are not effectively mitigated by existing phase delay controllers, especially with multiple converters and varying environmental factors.
Innovation Solution
A power management integrated circuit design that includes a clock generator and multiple phase delay controllers generating supply clocks with different phases for each switching converter, utilizing digital logic circuits and phase frequency detectors to adjust and synchronize clock phases accurately, reducing EMI and improving precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple switching converters operate at constant frequency through internal clock generators, then voltage conversion is achieved, but electromagnetic interference (EMI) occurs and input filter capacitor capacitance increases
Solution Approach 1:
The patent applies dynamics by making the operating frequency of switching converters variable rather than constant. Multiple clock generators produce clocks at different frequencies, and phase delay controllers adjust the frequency of each converter dynamically. This frequency variation prevents simultaneous switching of multiple converters, thereby reducing EMI while maintaining voltage conversion capability.
Solution Approach 2:
The patent implements periodic action through phase delay controllers that periodically adjust the operating frequency of each switching converter. The controllers create periodic frequency variations that ensure converters operate at different phases, preventing simultaneous switching events that cause EMI while maintaining continuous power conversion.
2Object-affected harmful factors
If separate phase delay controllers are used to adjust operating clocks, then EMI is reduced, but phase adjustment accuracy is insufficient due to increased number of controllers and environmental factors
Solution Approach 1:
The patent implements feedback mechanisms where phase delay controllers continuously monitor and adjust the phase and frequency of clocks supplied to each switching converter. This feedback ensures that even with multiple converters and environmental variations, the phase adjustment remains accurate and EMI is effectively reduced.
Solution Approach 2:
The patent changes the parameters of clock signals by using multiple clock generators that produce clocks with different frequencies and phases. Phase delay controllers further adjust these parameters dynamically, allowing precise control over the operating conditions of each converter to maintain accuracy despite environmental factors.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A power management integrated circuit including: a clock generator that generates an input clock; a first phase delay controller that delays the input clock by a first phase and outputs a first supply clock to a first switching converter; a second phase delay controller that delays the input clock by a second phase and outputs a second supply clock to a second switching converter; and a third phase delay controller that delays the input clock by a third phase and outputs a third supply clock to a third switching converter, wherein the first phase, the second phase and the third phase have different phases from each other.