PMIC Voltage Adjustment for Display Power and Artifact Reduction
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Solution Overview
Problem
Existing electronic displays face challenges in efficiently managing power consumption, particularly in reducing unwanted DC voltage offsets and AC noise, which can lead to increased power usage and display artifacts.
Innovation Solution
The implementation of a power management integrated circuit (PMIC) with image data reference voltage adjustment circuitry and a dedicated timing controller, which generates clock signals to improve frequency accuracy and reduce the frequency range of switched voltages, thereby minimizing power consumption and artifacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the display operates at full power to maintain image quality, then display performance is improved, but power consumption increases
Solution Approach 1:
The PMIC dynamically adjusts supply voltages based on operating conditions and throttle mode signals, transitioning between different power states to optimize the balance between display performance and power consumption
Solution Approach 2:
The system changes voltage parameters (supply voltages to switching converters) in response to throttle mode control signals, allowing the display to operate at reduced power while maintaining acceptable performance
2Speed
If switching converters operate at high frequency to improve response time, then response speed is improved, but power consumption and AC noise increase
Solution Approach 1:
The dedicated timing controller generates clock signals with optimized frequencies for switching converters, using periodic action to balance response time requirements with power consumption and noise reduction
3Speed
If switching converters operate at high frequency to improve response time, then response speed is improved, but AC noise and display artifacts increase
Solution Approach 1:
The timing controller optimizes clock signal frequencies to reduce AC noise and display artifacts while maintaining adequate response time through carefully selected periodic operation
4Device complexity
If voltage offsets are not compensated, then circuit complexity is reduced, but image quality and display performance deteriorate
Solution Approach 1:
The PMIC includes voltage offset compensation circuitry that uses feedback mechanisms to detect and correct voltage offsets, maintaining image quality without requiring complex external compensation circuits
5Reliability
If multiple supply voltages are generated to improve display performance, then display performance is improved, but power consumption increases
Solution Approach 1:
The PMIC dynamically adjusts multiple supply voltages based on operating conditions and throttle mode signals, reducing voltages when high performance is not required to minimize power consumption
Data Source
AI summary
A power management integrated circuit (PMIC) of an electronic display may include image data reference voltage adjustment circuitry, a negative supply voltage generator that may generate a negative supply voltage with multiple negative supply voltages, and/or a dedicated timing controller. The image data reference voltage adjustment circuitry may tune image data reference voltages for generating programming voltages based on receiving an indication of an undesired direct current (DC) voltage offset, an undesired alternating current (AC) noise, or both. The image data reference voltage adjustment circuitry may receive the indication from a display panel of the electronic display. The negative supply voltage generator may elevate a voltage of the negative supply voltage to reduce a power consumption of the electronic display. The dedicated timing controller may improve (e.g., reduce length of) a frequency range of one or more switched voltages of the PMIC to reduce front of screen artifacts.