PMOS Output Circuit Biasing for High External Voltage Leakage
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Solution Overview
Problem
Existing semiconductor integrated circuits experience transient leakage currents when receiving an external voltage higher than their own power supply voltage, particularly affecting P-channel MOS (PMOS) transistors in output circuits due to delayed gate voltage changes.
Innovation Solution
The semiconductor integrated circuit includes PMOS transistors connected in series with a gate driving mechanism that accelerates voltage changes by using a control signal, power supply voltage, and external voltage to manage the gate voltage of PMOS transistors, reducing leakage currents through a bias voltage generating circuit and critical voltage thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate voltage of PMOS transistors is changed slowly to maintain stability, then transient leakage currents are reduced, but the response time to voltage changes increases
Solution Approach 1:
The patent applies preliminary action by proactively detecting when an external voltage higher than the power supply voltage is applied to the external terminal, and in advance adjusting the gate voltage of the PMOS transistor to match the external voltage level. This preemptive voltage adjustment prevents the transistor from entering breakdown conditions before they occur, rather than reacting after the problem arises. The control circuit monitors the voltage differential and prepares the gate voltage in advance to maintain proper transistor operation during the transition.
2Speed
If the gate voltage changes quickly to improve response time, then transient leakage currents increase, but the response speed improves
Solution Approach 1:
The patent implements dynamics by making the gate voltage adjustment process adaptive and conditional rather than fixed. The control circuit dynamically determines the appropriate gate voltage based on real-time detection of the external voltage level and the power supply voltage differential. When a high external voltage is detected, the system dynamically adjusts the gate voltage to prevent breakdown; when normal operating conditions exist, the system maintains standard voltage levels. This dynamic adaptation allows optimal performance across varying operating conditions without generating unnecessary leakage currents.
3Device complexity
If a simple voltage feedback mechanism is used to control PMOS gate voltage, then device complexity is reduced, but control precision over transient currents decreases
Solution Approach 1:
The patent introduces an intermediary control circuit that acts as a mediator between the external terminal voltage and the PMOS transistor gate. This intermediary circuit detects the external voltage level and the power supply voltage, compares them to determine if a breakdown-risk condition exists, and then appropriately adjusts the gate voltage. The intermediary structure provides precise control over the gate voltage without requiring direct complex circuitry at the transistor level, achieving reliable leakage current control through a dedicated control layer that simplifies the overall device architecture while maintaining high precision.
Data Source
AI summary
A semiconductor integrated circuit includes: a power supply terminal that receives a power supply voltage; an external terminal; an output PMOS transistor connected between the power supply terminal and the external terminal; an auxiliary PMOS transistor connected between a gate of the output PMOS transistor and the external terminal; and a bias voltage generating circuit connected to a gate of the auxiliary PMOS transistor. The bias voltage generating circuit supplies a voltage lower than the power supply voltage to the gate of the auxiliary PMOS transistor, if it is necessary to maintain an OFF state of the output PMOS transistor by supplying an external voltage received at the external terminal to the gate of the output PMOS transistor.