PMOS Input Stage Biasing for Rail-to-Rail Offset Stability
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Solution Overview
Problem
PMOS transistors in circuit input stages are susceptible to negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI), leading to unbalanced threshold voltage shifts and offset voltages that exceed circuit specifications, particularly in rail-to-rail circuits.
Innovation Solution
Implementing PMOS source followers as voltage level shifters and controlling bias currents to maintain equal source-to-gate voltage across PMOS transistors, using current-switched configurations to cancel NBTI effects by keeping bias currents approximately the same throughout the input signal range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PMOS transistors are used in rail-to-rail input stages to detect low-side input common mode range, then the circuit can handle a wider input voltage range, but NBTI and PBTI effects cause unbalanced threshold voltage shifts and offset voltage exceeds specifications
Solution Approach 1:
The patent introduces an intermediary circuit block between the PMOS differential pair and the rest of the amplifier that actively compensates for NBTI-induced offset voltage. This intermediary mechanism monitors and corrects the threshold voltage shifts in real-time, allowing the PMOS transistors to operate in the wide input common mode range without compromising offset voltage stability.
Solution Approach 2:
The patent dynamically adjusts bias currents and voltage levels to compensate for NBTI effects. By changing operating parameters such as gate-source voltage and bias current magnitude, the circuit maintains balanced threshold voltages across PMOS transistors even under varying input conditions and temperature, thus preserving offset voltage stability while extending input range.
2Reliability
If bias current is increased to reduce NBTI effects, then threshold voltage stability improves, but power consumption increases
Solution Approach 1:
The patent employs dynamic biasing where the bias current is adjusted based on operating conditions rather than being fixed. The circuit adapts the bias current level to match the actual NBTI stress conditions, applying higher current only when needed to counteract NBTI effects, thereby maintaining threshold voltage stability while minimizing unnecessary power consumption during normal operation.
Solution Approach 2:
The patent implements periodic calibration or compensation cycles where bias currents are adjusted to counteract accumulated NBTI effects. Instead of continuously high bias current, the system uses controlled periodic adjustments to maintain threshold voltage stability, reducing average power consumption while ensuring reliability when needed.
Data Source
AI summary
Examples of input stages of circuits are configured to reduce both negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) in PMOS transistors therein. Current-switched PMOS source follower transistors and a low-side NMOS differential pair is used to process a lower range of a rail-to-rail input signal range of a circuit. A PMOS source follower is disposed between the positive input of the circuit and the positive input of the low-side NMOS differential pair. Another PMOS source follower is disposed between the negative input of the circuit and the negative input of the low-side NMOS differential pair. Various arrangements are provided for generating and maintaining the bias currents of the two PMOS source followers to be approximately the same through the entire lower input signal range.