Memory Write Circuit Using PMOS Bitline Pull-Up for Full VDD
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Solution Overview
Problem
Memory write circuits face challenges in maintaining stability and writability due to static noise margin degradation and process variations, which affect bit cell yield and functionality.
Innovation Solution
The implementation of a write circuit that couples bitlines to a power supply using PMOS transistors instead of NMOS transistors, allowing bitlines to reach full VDD voltage and avoiding dynamic nodes that cause charge sharing, thereby enhancing static noise margin and writability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If NMOS transistors are used to couple bitlines to power supply, then device complexity is reduced, but voltage drop occurs between VDD and bitlines preventing full VDD voltage level
Solution Approach 1:
The patent changes the transistor type parameter from NMOS to PMOS for the power supply coupling transistors. PMOS transistors have different electrical characteristics that eliminate the voltage drop issue inherent in NMOS transistors, allowing bitlines to reach full VDD voltage level while maintaining acceptable device complexity
Solution Approach 2:
Instead of using NMOS transistors (n-type) to couple bitlines to VDD, the patent inverts the approach by using PMOS transistors (p-type). This inversion of the transistor type resolves the voltage drop problem because PMOS transistors can pass strong logic 1 signals to the bitlines without significant voltage loss
2Area of stationary object
If dynamic nodes share charge across NMOS transistors, then circuit area is reduced, but bitline voltage cannot reach full VDD level
Solution Approach 1:
The patent extracts or removes the problematic dynamic nodes that share charge across NMOS transistors from the critical bitline path. By eliminating these charge-sharing nodes, the bitlines can be directly driven to full VDD levels without being pulled down by shared charge, while the overall circuit area remains acceptable through optimized layout
3Ease of manufacture
If conventional write circuits are used, then manufacturing process is simpler, but static noise margin and writability degrade due to process variation
Solution Approach 1:
The patent changes key circuit parameters including transistor types (using PMOS for pull-up, NMOS for pull-down), voltage levels (ensuring full VDD on bitlines), and drive strength ratios. These parameter changes increase the static noise margin and writability to overcome process variation effects, while the manufacturing process remains compatible with standard CMOS technology
Data Source
AI summary
Various implementations provide systems and methods for writing data to memory bit cells. An example implementation includes a write circuit that couples both a bitline and a complementary bitline to power (VDD) by positive-channel metal oxide semiconductor (PMOS) transistors. By using PMOS transistors instead of NMOS transistors at the applicable nodes, such implementations may avoid a voltage drop between VDD and the bitlines, thereby allowing the bitlines to reach a substantially full VDD voltage level when appropriate. Additionally, various implementations avoid dynamic nodes that share charge across NMOS transistors, thereby allowing a given bitline to reach a substantially full VDD voltage level when appropriate. Accordingly, some implementations may experience higher levels of writability and static noise margin than other implementations.