PMOS Transistor Boron Out-Diffusion Barrier

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In PMOS transistors, the high diffusivity of Boron ions during the annealing process after low-energy ion implantation leads to out-diffusion, preventing impurities from reaching the desired implantation level, which slows down the transistor speed.

Innovation Solution

A semiconductor device and fabrication method that includes forming a silicon oxide nitride layer on the source/drain area to prevent Boron ion out-diffusion, using a nitrogen plasma process to create a barrier that maintains impurity density during annealing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If low-energy ion implantation is used to achieve reduced junction depth, then the junction depth is reduced to about 20 nm, but Boron ions out-diffuse during annealing due to high diffusivity, preventing impurities from reaching the desired implantation level and slowing down transistor speed

Engineering Contradiction:
Improvejunction depthVSAvoidtransistor speed
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A silicon oxide nitride layer is introduced as an intermediary barrier between the semiconductor substrate and the external environment. This layer specifically blocks Boron ion out-diffusion during annealing while allowing the low-energy implantation process to achieve the desired shallow junction depth of about 20 nm, thereby preventing transistor speed degradation

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention uses a composite silicon oxide nitride layer that combines properties of both oxide and nitride materials. This composite structure provides superior Boron ion blocking capability compared to single-material layers, enabling the maintenance of impurity density at the shallow junction depth while preventing out-diffusion during thermal processing

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The silicon oxide nitride layer effectively prevents Boron ion out-diffusion, ensuring the PMOS transistor retains its operation speed and prevents increased extension resistance, thereby improving semiconductor device performance.

Implementation Method 1

forming a silicon oxide nitride layer on the source/drain area to prevent Boron ion out-diffusion, using a nitrogen plasma process to create a barrier

Methodology Applied
Scientific EffectPlasma process: Plasma

Implementation Method 2

in an annealing process for activating the high density Boron ions in source/drain area 133

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 3

Boron ions may be out-diffused even if the ion implantation process is performed with a low ion implantation energy

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 4

by implanting high density impurities, such as Boron ions, in source/drain area 133 at a low energy of about 1 KeV to 5 KeV

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS8466030B2Semiconductor device and fabricating method thereof
Publication Date: 2013.06.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8466030B2 patent drawing
  • US8466030B2 patent drawing
  • US8466030B2 patent drawing

AI summary

A semiconductor device, such as a positive channel metal-oxide semiconductor (PMOS) transistor, and a fabricating method thereof are provided. The semiconductor device includes: a gate insulation layer and a gate electrode, a semiconductor substrate, a spacer formed on side walls of the gate insulation layer and the gate electrode, a lightly doped drain (LDD) area formed on the semiconductor substrate at both sides of the gate electrode, a source/drain area formed on the semiconductor substrate at both sides of the gate electrode, and an oxide-nitride layer formed on the gate electrode and on the source/drain area.