Selective Carbon Nitrogen Co-Implants for PMOS Transistors
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Solution Overview
Problem
The scaling down of CMOS integrated circuits to achieve higher densities and faster transistors leads to issues such as time-dependent threshold voltage changes and degradation of PMOS transistor performance due to stress memorization technique (SMT) processing, which increases short channel effects and reduces hole mobility, necessitating additional costly processing steps to avoid degradation.
Innovation Solution
Selective co-implants of carbon, nitrogen, and optionally indium in the p-type lightly doped drain regions of PMOS transistors, allowing the SMT layer to remain during source/drain annealing without degrading PMOS performance, and varying gate dielectric thickness and composition across the IC to differentiate between core and non-core transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SMT layer is removed before source/drain annealing to avoid PMOS degradation, then PMOS performance is maintained, but additional costly processing steps are required
Solution Approach 1:
The patent applies carbon and nitrogen co-implants to convert the harmful effect of the SMT layer (which causes boron diffusion and PMOS degradation) into a beneficial outcome. The carbon and nitrogen implants modify the PLDD regions to suppress boron diffusion, allowing the SMT layer to remain during annealing without degrading PMOS performance, thus eliminating the need for additional processing steps to remove the SMT layer
2Power
If carbon and nitrogen co-implants are applied to all PMOS transistors, then PMOS drive current is enhanced, but core PMOS transistors experience increased polysilicon depletion effects and degraded performance
Solution Approach 1:
The patent applies carbon and nitrogen co-implants selectively only to non-core PMOS transistors (such as I/O transistors) that benefit from enhanced drive current, while excluding core PMOS transistors that would experience degraded performance due to polysilicon depletion effects. This local differentiation allows each transistor type to receive appropriate treatment based on its specific performance requirements
3Adaptability or versatility
If gate dielectric thickness is varied across the IC, then differentiation between core and non-core transistors is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent implements different gate dielectric thicknesses for core and non-core PMOS transistors to optimize their respective performances. Non-core transistors receive thicker gate dielectrics to withstand higher voltages, while core transistors have thinner gate dielectrics for faster switching. This local differentiation is achieved through selective epitaxial growth that allows different dielectric thicknesses in different regions of the same wafer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances PMOS drive current, reduces gate-to-drain capacitance, and mitigates dopant diffusion, while allowing the SMT layer to remain during annealing, eliminating the need for extra processing steps and improving transistor performance without significant mobility degradation.
Implementation Method 1
selective co-implants in at least their PLDD regions comprising carbon and nitrogen
Implementation Method 2
allowing the SMT layer to remain during source/drain annealing
Data Source
AI summary
A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate.The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.